220.127.116.11 Quad Synchronous Serial Interface (QSSI)
QSSI is a bidirectional communications interface that converts data between parallel and serial. The QSSI module performs serial-to-parallel conversion on data received from a peripheral device and performs parallel-to-serial conversion on data transmitted to a peripheral device. The QSSI module can be configured as either a master or slave device. As a slave device, the QSSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The QSSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the input clock of the QSSI module. Bit rates are generated based on the input clock, and the maximum bit rate is determined by the connected peripheral.
The four QSSI modules each support the following features:
- Four QSSI channels with advanced, bi-SSI, and quad-SSI functionality
- Programmable interface operation for Freescale SPI or TI synchronous serial interfaces in legacy mode. Support for Freescale interface in Bi- and Quad-SSI mode.
- Master or slave operation
- Programmable clock bit rate and prescaler
- Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
- Programmable data frame size from 4 to 16 bits
- Internal loopback test mode for diagnostic/debug testing
- Standard FIFO-based interrupts and end-of-transmission interrupt
- Efficient transfers using µDMA
- Separate channels for transmit and receive
- Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains four entries
- Transmit single request asserted when there is space in the FIFO; burst request asserted when four or more entries are available to be written in the FIFO
- Maskable µDMA interrupts for receive and transmit complete
- Global alternate clock (ALTCLK) resource or system clock (SYSCLK) can be used to generate baud clock.