JAJSE27 October 2017 MSP432E401Y
The PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency and enables the PLL to drive the output. The PLL is controlled using the PLLFREQ0, PLLFREQ1, and PLLSTAT registers. Changes made to these registers do not become active until after the NEWFREQ bit in the RSCLKCFG register is enabled. The clock source for the main PLL is selected by configuring the PLLSRC field in the Run and Sleep Clock Configuration (RSCLKCFG) register. The PLL allows for the generation of system clock frequencies in excess of the reference clock provided. The reference clocks for the PLL are the PIOSC and the MOSC.
The PLL is controlled by two registers, PLLFREQ0 and PLLFREQ1. The PLL VCO frequency (fVCO) is determined through Equation 1.
The Q and N values are programmed in the PLLFREQ1 register. To reduce jitter, program MFRAC to 0x0.
When the PLL is active, the system clock frequency (SysClk) is calculated using Equation 2.
The PLL system divisor factor (PSYSDIV) must be set as 1. Table 5-6 lists examples of the system clock frequency.
|fVCO (MHz)||Q||PSYSDIV + 1||System Clock (SYSCLK) Frequency (MHz)|
If the main oscillator provides the clock reference to the PLL, the translation provided by hardware and used to program the PLL is available for software in the PLL Frequency n (PLLFREQn) registers. The internal translation provides a translation within ±1% of the targeted PLL VCO frequency. Table 5-7 shows the actual PLL frequency and error for a given crystal choice.
Table 5-7 provides examples of the programming expected for the PLLFREQ0 and PLLFREQ1 registers. The CRYSTAL FREQUENCY column specifies the input crystal frequency and the PLL FREQUENCY column displays the PLL frequency given the values of MINT and N, when Q = 0.
|CRYSTAL FREQUENCY (MHz)||MINT||N||REFERENCE FREQUENCY (MHz)(2)||PLL FREQUENCY (MHz)|
|DECIMAL VALUE||HEXADECIMAL VALUE|