JAJS198L October   2006  – January 2020 OPA211


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      入力電圧ノイズ密度と周波数との関係
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions: OPA211
    2.     Pin Functions: OPA2211
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA211 and OPA211A
    5. 7.5 Thermal Information: OPA2211 and OPA2211A
    6. 7.6 Electrical Characteristics: Standard Grade OPAx211A
    7. 7.7 Electrical Characteristics: High-Grade OPAx211
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Total Harmonic Distortion Measurements
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Operating Voltage
      2. 9.1.2 Input Protection
      3. 9.1.3 Noise Performance
      4. 9.1.4 Basic Noise Calculations
      5. 9.1.5 EMI Rejection
      6. 9.1.6 EMIRR +IN Test Configuration
      7. 9.1.7 Electrical Overstress
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 SON Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. TINA-TI™ (無料のダウンロード・ソフトウェア)
        2. TI Precision Designs
        3. WEBENCH® Filter Designer
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 サポート・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報



SON Layout Guidelines

The OPA211 is offered in an SON-8 package (also known as SON). The SON package is a QFN package with lead contacts on only two sides of the bottom of the package. This leadless package maximizes board space and enhances thermal and electrical characteristics through an exposed pad.

SON packages are physically small, and have a smaller routing area, improved thermal performance, and improved electrical parasitics. Additionally, the absence of external leads eliminates bent-lead issues.

The SON package can be easily mounted using standard printed circuit board (PCB) assembly techniques. See the QFN/SON PCB Attachment application note and the Quad Flatpack No-Lead Logic Packages application report, both available for download at www.ti.com.


The exposed leadframe die pad on the bottom of the package must be connected to V–. Soldering the thermal pad improves heat dissipation and enables specified device performance.

The exposed leadframe die pad on the SON package should be soldered to a thermal pad on the PCB. A mechanical drawing showing an example layout is attached at the end of this data sheet. Refinements to this layout may be necessary based on assembly process requirements. Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are intended for use with thermal vias that connect the leadframe die pad to the heat sink area on the PCB.

Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.