JAJSGL4 December   2018 OPA2313-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      EMIRR IN+と周波数との関係
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions: OPA2313-Q1
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: 5.5 V
    6. 6.6 Electrical Characteristics: 1.8 V
    7. 6.7 Typical Characteristics: Tables of Graphs
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Rail-to-Rail Input
      3. 7.3.3 Rail-to-Rail Output
      4. 7.3.4 Common-Mode Rejection Ratio (CMRR)
      5. 7.3.5 Capacitive Load and Stability
      6. 7.3.6 EMI Susceptibility and Input Filtering
      7. 7.3.7 Input and ESD Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics: Tables of Graphs

Table 1. Characteristic Performance Measurements

TITLE FIGURE
Open-Loop Gain and Phase vs Frequency Figure 1
Open-Loop Gain vs Temperature Figure 2
Quiescent Current vs Supply Voltage Figure 3
Quiescent Current vs Temperature Figure 4
Offset Voltage Production Distribution Figure 5
Offset Voltage Drift Distribution Figure 6
Offset Voltage vs Common-Mode Voltage (Maximum Supply) Figure 7
Offset Voltage vs Temperature Figure 8
CMRR and PSRR vs Frequency (RTI) Figure 9
CMRR and PSRR vs Temperature Figure 10
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V) Figure 11
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V) Figure 12
Input Voltage Noise vs Common-Mode Voltage (5.5 V) Figure 13
Input Bias and Offset Current vs Temperature Figure 14
Open-Loop Output Impedance vs Frequency Figure 15
Maximum Output Voltage vs Frequency and Supply Voltage Figure 16
Output Voltage Swing vs Output Current (over Temperature) Figure 17
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V) Figure 18
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (5.5 V) Figure 19
Small-Signal Overshoot vs Load Capacitance Figure 20
Phase Margin vs Capacitive Load Figure 21
Small-Signal Step Response, Noninverting (1.8 V) Figure 22
Small-Signal Step Response, Noninverting ( 5.5 V) Figure 23
Large-Signal Step Response, Noninverting (1.8 V) Figure 24
Large-Signal Step Response, Noninverting ( 5.5 V) Figure 25
Positive Overload Recovery Figure 26
Negative Overload Recovery Figure 27
No Phase Reversal Figure 28
Channel Separation vs Frequency (Dual) Figure 29
THD+N vs Amplitude (G = +1, 2 kΩ, 10 kΩ) Figure 30
THD+N vs Amplitude (G = –1, 2 kΩ, 10 kΩ) Figure 31
THD+N vs Frequency (0.5 VRMS, G = +1, 2 kΩ, 10 kΩ) Figure 32
EMIRR IN+ vs Frequency Figure 33