The OPAx835 family of bipolar-input operational amplifiers offers excellent bandwidth of 56 MHz with ultra-low THD of 0.00003% at 1 kHz. The device can swing to within 200 mV of the supply rails while driving a 2-kΩ load. The input common-mode of the amplifier can swing to 200 mV below the negative supply rail. This level of performance is achieved at 250 µA of quiescent current per amplifier channel.
When the primary design goal is a linear amplifier, with high CMRR, it is important to not violate the input common-mode voltage range (VICR) of an op amp.
The common-mode input range specifications in the table data use CMRR to set the limit. The limits are selected to ensure CMRR will not degrade more than 3 dB below the CMRR limit if the input voltage is kept within the specified range. The limits cover all process variations, and most parts will be better than specified. The typical specifications are 0.2 V below the negative rail and 1.1 V below the positive rail.
Assuming the op amp is in linear operation, the voltage difference between the input pins is small (ideally 0 V); and the input common-mode voltage is analyzed at either input pin with the other input pin assumed to be at the same potential. The voltage at VIN+ is simple to evaluate. In noninverting configuration, Figure 53, the input signal, VIN, must not violate the VICR. In inverting configuration, as shown in Figure 54, the reference voltage, VREF, must be within the VICR.
The input voltage limits have fixed headroom to the power rails and track the power supply voltages. For one 5-V supply, the linear input voltage ranges from –0.2 V to 3.9 V and –0.2 V to 1.6 V for a 2.7-V supply. The delta headroom from each power supply rail is the same in either case: –0.2 V and 1.1 V.
The OPA835 and OPA2835 devices are rail-to-rail output (RRO) op amps. Rail-to-rail output typically means that the output voltage swings within a couple hundred millivolts of the supply rails. There are different ways to specify this: one is with the output still in linear operation and another is with the output saturated. Saturated output voltages are closer to the power supply rails than linear outputs, but the signal is not a linear representation of the input. Linear output is a better representation of how well a device performs when used as a linear amplifier. Saturation and linear operation limits are affected by the output current, where higher currents lead to more loss in the output transistors.
The specification tables list linear and saturated output voltage specifications with 2-kΩ load. Figure 11 and Figure 37 show saturated voltage-swing limits versus output load resistance, and Figure 12 and Figure 38 show the output saturation voltage versus load current. Given a light load, the output voltage limits have nearly constant headroom to the power rails and track the power supply voltages. For example, with a 2-kΩ load and a single 5-V supply, the linear output voltage ranges from 0.15 V to 4.8 V and ranges from 0.15 V to 2.5 V for a 2.7-V supply. The delta from each power supply rail is the same in either case: 0.15 V and 0.2 V.
With devices like the OPA835 and OPA2835 where the input range is lower than the output range, typically the input will limit the available signal swing only in noninverting gain of 1. Signal swing in noninverting configurations in gains > +1 and inverting configurations in any gain is typically limited by the output voltage limits of the op amp.
The OPA835 and OPA2835 devices include a power-down mode. Under logic control, the amplifiers can switch from normal operation to a standby current of < 1.5 µA. When the PD pin is connected high, the amplifier is active. Connecting PD pin low disables the amplifier and places the output in a high-impedance state. When the amplifier is configured as a unity-gain buffer, the output stage is in a high dc-impedance state. To protect the input stage of the amplifier, the devices use internal, back-to-back ESD diodes between the inverting and noninverting input pins. This configuration creates a parallel low-impedance path from the amplifier output to the noninverting pin when the differential voltage between the pins exceeds a diode voltage drop. When the op amp is configured in other gains, the feedback (RF) and gain (RG) resistor network forms a parallel load.
The PD pin must be actively driven high or low and must not be left floating. If the power-down mode is not used, PD must be tied to the positive supply rail.
PD logic states are TTL with reference to the negative supply rail, VS–. When the op amp is powered from a single-supply and ground, driven from logic devices with similar VDD voltages to the op amp do not require any special consideration. When the op amp is powered from a split supply, with VS– below ground, an open-collector type of interface with a pullup resistor is more appropriate. Pullup resistor values must be lower than 100 kΩ. Additionally, the drive logic must be negated due to the inverting action of an open-collector gate.
The OPA835 and OPA2835 devices are designed for the nominal value of RF to be 2 kΩ in gains other than +1. This gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. It also loads the amplifier. For example; in gain of 2 with RF = RG = 2 kΩ, RG to ground, and VOUT = 4 V, 1 mA of current will flow through the feedback path to ground. In gain of +1, RG is open and no current will flow to ground. In low-power applications, it is desirable to reduce the current in the feedback path by increasing the gain-setting resistors values. Using larger value gain resistors has two primary side effects (other than lower power) due to their interaction with parasitic circuit capacitance.
Figure 55 shows the small-signal frequency response on OPA835EVM for noninverting gain of 2 with RF and RG equal to 2 kΩ, 10 kΩ, and 100 kΩ. The test was done with RL = 2 kΩ. Due to loading effects of RL, lower RL values may reduce the peaking, but higher values will not have a significant effect.
As expected, larger value gain resistors cause lower bandwidth and peaking in the response (peaking in frequency response is synonymous with overshoot and ringing in pulse response). Adding 1-pF capacitors in parallel with RF helps compensate the phase margin and restores flat frequency response. Figure 56 shows the test circuit.
The OPA835 and OPA2835 devices drive up to a nominal capacitive load of 10 pF on the output with no special consideration. When driving capacitive loads greater than 10 pF, TI recommends using a small resistor (RO) in series with the output as close to the device as possible. Without RO, output capacitance interacts with the output impedance of the amplifier causing phase shift in the loop gain of the amplifier that will reduce the phase margin. This will cause peaking in the frequency response and overshoot and ringing in the pulse response. Interaction with other parasitic elements may lead to instability or oscillation. Inserting RO will isolate the phase shift from the loop gain path and restore the phase margin; however RO can limit the bandwidth slightly.
To facilitate testing with common lab equipment, the OPA835 EVM ( see OPA835DBV and OPA836DBV EVM User's Guide (SLOU314) ) is built to allow split-supply operation. This configuration eases lab testing because the mid-point between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum analyzers and other lab equipment have inputs and outputs with a ground reference.
Figure 58 shows a simple noninverting configuration analogous to Figure 53 with ±2.5-V supply and VREF equal to ground. The input and output will swing symmetrically around ground. For ease of use, split supplies are preferred in systems where signals swing around ground.
Often, newer systems use a single power supply to improve efficiency and reduce the cost of the power supply. OPA835 and OPA2835 devices are designed for use with single-supply power operation and can be used with single-supply power with no change in performance from split supply, as long as the input and output are biased within the linear operation of the device.
To change the circuit from split supply to single-supply, level shift all voltages by ½ the difference between the power supply rails. For example, changing from ± 2.5-V split supply to 5-V single-supply is shown in Figure 59.
A practical circuit will have an amplifier or other circuit providing the bias voltage for the input, and the output of this amplifier stage provides the bias for the next stage.
Figure 60 shows a typical noninverting amplifier circuit. With 5-V single-supply, a mid-supply reference generator is needed to bias the negative side through RG. To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG. For example if gain of 2 is required and RF = 2 kΩ, select RG = 2 kΩ to set the gain, and R1 = 1 kΩ for bias current cancellation. The value for C is dependent on the reference, and TI recommends a value of at least 0.1 µF to limit noise.
Figure 61 shows a similar noninverting single-supply scenario with the reference generator replaced by the Thevenin equivalent using resistors and the positive supply. RG’ and RG” form a resistor divider from the 5-V supply and are used to bias the negative side with the parallel sum equal to the equivalent RG to set the gain. To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG’ in parallel with RG” (R1= RF || RG’ || RG”). For example, if a gain of 2 is required and RF = 2 kΩ, selecting RG’ = RG” = 4 kΩ gives equivalent parallel sum of 2 kΩ, sets the gain to 2, and references the input to mid supply (2.5 V). R1 is set to 1 kΩ for bias current cancellation. The resistor divider costs less than the 2.5V reference in Figure 60 but may increase the current from the 5-V supply.
Figure 62 shows a typical inverting-amplifier circuit. With a 5-V single-supply, a mid-supply reference generator is needed to bias the positive side through R1. To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of –2 is required and RF = 2 kΩ, select RG = 1 kΩ to set the gain and R1 = 667 Ω for bias current cancellation. The value for C is dependent on the reference, but TI recommends a value of at least 0.1 µF to limit noise into the op amp.
Figure 63 shows a similar inverting single-supply scenario with the reference generator replaced by the Thevenin equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5-V supply and are used to bias the positive side. To cancel the voltage offset that would otherwise be caused by the input bias currents, set the parallel sum of R1 and R2 equal to the parallel sum of RF and RG. C must be added to limit coupling of noise into the positive input. For example, if gain of –2 is required and RF = 2 kΩ, select RG = 1 kΩ to set the gain. R1 = R2 = 667 Ω for mid-supply voltage bias and for op-amp input-bias current cancellation. A good value for C is 0.1 µF. The resistor divider costs less than the 2.5-V reference in Figure 62 but may increase the current from the 5-V supply.