SLOS713I January   2011  – August 2016 OPA2835 , OPA835

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. OPA835-Related Devices
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA835
    5. 7.5 Thermal Information: OPA2835
    6. 7.6 Electrical Characteristics: VS = 2.7 V
    7. 7.7 Electrical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 2.7 V
    9. 7.9 Typical Characteristics: VS = 5 V
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Low-Power Applications and the Effects of Resistor Values on Bandwidth
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.25 V to ±2.75 V)
      2. 8.4.2 Single-Supply Operation (2.5 V to 5.5 V)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Noninverting Amplifier
      2. 9.1.2  Inverting Amplifier
      3. 9.1.3  Instrumentation Amplifier
      4. 9.1.4  Attenuators
      5. 9.1.5  Single-Ended to Differential Amplifier
      6. 9.1.6  Differential to Single-Ended Amplifier
      7. 9.1.7  Differential-to-Differential Amplifier
      8. 9.1.8  Gain Setting With OPA835 RUN Integrated Resistors
      9. 9.1.9  Pulse Application With Single-Supply
      10. 9.1.10 ADC Driver Performance
    2. 9.2 Typical Application
      1. 9.2.1 Audio Frequency Performance
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Filters
        1. 9.2.2.1 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
      2. 12.2.2 Related Links
      3. 12.2.3 Receiving Notification of Documentation Updates
      4. 12.2.4 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS– to VS+ Supply voltage 5.5 V
VI Input voltage VS– – 0.7 VS+ + 0.7 V
VID Differential input voltage 1 V
II Continuous input current 0.85 mA
IO Continuous output current 60 mA
Continuous power dissipation See Thermal Information: OPA835 and Thermal Information: OPA2835
TJ Maximum junction temperature 150 °C
TA Operating free-air temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±6000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS+ Single supply voltage 2.5 5 5.5 V
TA Ambient temperature –40 25 125 °C

7.4 Thermal Information: OPA835

THERMAL METRIC(1) OPA835 UNIT
DBV
(SOT23-6)
RUN
(QFN)
6 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 194 145.8 °C/W
RθJCtop Junction-to-case (top) thermal resistance 129.2 75.1 °C/W
RθJB Junction-to-board thermal resistance 39.4 38.9 °C/W
ψJT Junction-to-top characterization parameter 25.6 13.5 °C/W
ψJB Junction-to-board characterization parameter 38.9 104.5 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

7.5 Thermal Information: OPA2835

THERMAL METRIC(1) OPA2835 UNIT
D
(SOIC)
DGS
(VSSOP)
RUN
(QFN)
RMC
(UQFN)
8 PINS 10 PINS 10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 150.1 206 145.8 143.2 °C/W
RθJCtop Junction-to-case (top) thermal resistance 83.8 75.3 75.1 49.0 °C/W
RθJB Junction-to-board thermal resistance 68.4 96.2 38.9 61.9 °C/W
ψJT Junction-to-top characterization parameter 33.0 12.9 13.5 3.3 °C/W
ψJB Junction-to-board characterization parameter 67.9 94.6 104.5 61.9 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

7.6 Electrical Characteristics: VS = 2.7 V

at VS+ = +2.7 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, VIN_CM = mid-supply – 0.5 V. TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
AC PERFORMANCE
Small-signal bandwidth VOUT = 100 mVPP, G = 1 51 MHz C
VOUT = 100 mVPP, G = 2 22.5
VOUT = 100 mVPP, G = 5 7.2
VOUT = 100 mVPP, G = 10 3
Gain-bandwidth product VOUT = 100 mVPP, G = 10 30 MHz C
Large-signal bandwidth VOUT = 1 VPP, G = 1 24 MHz C
Bandwidth for 0.1-dB flatness VOUT = 1 VPP, G = 2 4 MHz C
Slew rate, rise VOUT = 1 VSTEP, G = 2 110 V/µs C
Slew rate, fall VOUT = 1 VSTEP, G = 2 130 V/µs C
Rise time VOUT = 1 VSTEP, G = 2 9.5 ns C
Fall time VOUT = 1 VSTEP, G = 2 9 ns C
Settling time to 1%, rise VOUT = 1 VSTEP, G = 2 35 ns C
Settling time to 1%, fall VOUT = 1 VSTEP, G = 2 30 ns C
Settling time to 0.1%, rise VOUT = 1 VSTEP, G = 2 60 ns C
Settling time to 0.1%, fall VOUT = 1 VSTEP, G = 2 65 ns C
Settling time to 0.01%, rise VOUT = 1 VSTEP, G = 2 120 ns C
Settling time to 0.01%, rise VOUT = 1 VSTEP, G = 2 90 ns C
Overshoot/Undershoot VOUT = 1 VSTEP, G = 2 0.5%/0.2% C
Second-order harmonic distortion f = 10 kHz, VIN_CM = mid-supply – 0.5 V –133 dBc C
f = 100 kHz, VIN_CM = mid-supply – 0.5 V –110
f = 1 MHz, VIN_CM = mid-supply – 0.5 V –73
Third-order harmonic distortion f = 10 kHz, VIN_CM = mid-supply – 0.5 V –137 dBc C
f = 100 kHz, VIN_CM = mid-supply – 0.5 V –125
f = 1 MHz, VIN_CM = mid-supply – 0.5 V –78
Second-order intermodulation distortion f = 1 MHz, 200-kHz Tone Spacing,
VOUT Envelope = 1 VPP,
VIN_CM = mid-supply – 0.5 V
–75 dBc C
Third-order intermodulation distortion f = 1 MHz, 200-kHz Tone Spacing,
VOUT Envelope = 1 VPP,
VIN_CM = mid-supply – 0.5 V
–81 dBc C
Input voltage noise f = 100 kHz 9.3 nV/√Hz C
Voltage noise 1/f corner frequency 147 Hz C
AC PERFORMANCE (continued)
Input current noise f = 1 MHz 0.45 pA/√Hz C
Current noise 1/f corner frequency 14.7 kHz C
Overdrive recovery time, over/under Overdrive = 0.5 V 140/125 ns C
Closed-loop output impedance f = 100 kHz 0.028 Ω C
Channel-to-channel crosstalk (OPA2835) f = 10 kHz –120 dB C
DC PERFORMANCE
Open-loop voltage gain (AOL) 100 120 dB A
Input referred offset voltage TA = 25°C –500 ±100 500 µV A
TA = 0°C to 70°C –880 880 B
TA = –40°C to 85°C –1040 1040
TA = –40°C to 125°C –1850 1850
Input offset voltage drift(3) TA = 0°C to 70°C –8.5 ±1.4 8.5 µV/°C B
TA = –40°C to 85°C –9 ±1.5 9
TA = –40°C to 125°C –13.5 ±2.25 13.5
Input bias current(2) TA = 25°C 50 200 400 nA A
TA = 0°C to 70°C 47 410 B
TA = –40°C to 85°C 45 425
TA = –40°C to 125°C 45 530
Input bias current drift(3) TA = 0°C to 70°C –1.4 ±0.25 1.4 nA/°C B
TA = –40°C to 85°C –1.05 ±0.175 1.05
TA = –40°C to 125°C –1.1 ±0.185 1.1
Input offset current TA = 25°C –100 ±13 100 nA A
TA = 0°C to 70°C –100 ±13 100 B
TA = –40°C to 85°C –100 ±13 100
TA = –40°C to 125°C –100 ±13 100
Input offset current drift(3) TA = 0°C to 70°C –1.230 ±0.205 1.230 nA/°C B
TA = –40°C to 85°C –0.940 ±0.155 0.940
TA = –40°C to 125°C –0.940 ±0.155 0.940
INPUT
Common-mode input range low TA = 25°C, < 3 dB degradation in CMRR limit –0.2 0 V A
TA = –40°C to 125°C, < 3-dB degradation in CMRR limit –0.2 0 V B
Common-mode input range high TA = 25°C, < 3-dB degradation in CMRR limit 1.5 1.6 V A
TA = –40°C to 125°C, < 3-dB degradation in CMRR limit 1.5 1.6 V B
Common-mode rejection ratio 88 110 dB A
Input impedance common-mode 200 || 1.2 kΩ || pF C
Input impedance differential mode 200 || 1 kΩ || pF C
OUTPUT
Output voltage low TA = 25°C, G = 5 0.15 0.2 V A
TA = –40°C to 125°C, G = 5 0.15 0.2 V B
Output voltage high TA = 25°C, G = 5 2.45 2.5 V A
TA = –40°C to 125°C, G = 5 2.45 2.5 V B
Output saturation voltage, high/low TA = 25°C, G = 5 45/13 mV C
Output current drive TA = 25°C ±25 ±35 mA A
TA = –40°C to 125°C ±20 mA B
GAIN-SETTING RESISTORS (OPA835IRUN ONLY)
Resistor FB1 to FB2 DC resistance 2376 2400 2424 Ω A
Resistor FB2 to FB3 DC resistance 1782 1800 1818 Ω A
Resistor FB3 to FB4 DC resistance 594 600 606 Ω A
Resistor tolerance DC resistance –1% 1% A
Resistor temperature coefficient DC resistance < 10 PPM C
POWER SUPPLY
Specified operating voltage 2.5 5.5 V B
Quiescent operating current per amplifier TA = 25°C 175 245 340 µA A
TA = –40°C to 125°C 135 345 µA B
Power supply rejection (±PSRR) 88 105 dB A
POWER DOWN (PIN MUST BE DRIVEN)
Enable voltage threshold Specified on above VS–+ 2.1 V 1.4 2.1 V A
Disable voltage threshold Specified off below VS–+ 0.7 V 0.7 1.4 V A
Power-down pin bias current PD = 0.5 V 20 500 nA A
Power-down quiescent current PD = 0.5 V 0.5 1.5 µA A
Turnon time delay Time from PD = high to VOUT = 90% of final value 250 ns C
Turnoff time delay Time from PD = low to VOUT = 10% of original value 50 ns C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) Current is considered positive out of the pin.
(3) Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range.

7.7 Electrical Characteristics: VS = 5 V

at VS+ = +5 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply. TA = 25°C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
AC PERFORMANCE
Small-signal bandwidth VOUT = 100 mVPP, G = 1 56 MHz C
VOUT = 100 mVPP, G = 2 22.5
VOUT = 100 mVPP, G = 5 7.4
VOUT = 100 mVPP, G = 10 3.1
Gain-bandwidth product VOUT = 100 mVPP, G = 10 31 MHz C
Large-signal bandwidth VOUT = 2 VPP, G = 1 31 MHz C
Bandwidth for 0.1-dB flatness VOUT = 2 VPP, G = 2 14.5 MHz C
Slew rate, rise VOUT = 2-V Step, G = 2 160 V/µs C
Slew rate, fall VOUT = 2-V Step, G = 2 260 V/µs C
Rise time VOUT = 2-V Step, G = 2 10 ns C
Fall time VOUT = 2-V Step, G = 2 7 ns C
Settling time to 1%, rise VOUT = 2-V Step, G = 2 45 ns C
Settling time to 1%, fall VOUT = 2-V Step, G = 2 45 ns C
Settling time to 0.1%, rise VOUT = 2-V Step, G = 2 50 ns C
Settling time to 0.1%, fall VOUT = 2-V Step, G = 2 55 ns C
Settling time to 0.01%, rise VOUT = 2-V Step, G = 2 82 ns C
Settling time to 0.01%, fall VOUT = 2-V Step, G = 2 85 ns C
Overshoot/Undershoot VOUT = 2-V Step, G = 2 2.5%/1.5% C
Second-order harmonic distortion f = 10 kHz –135 dBc C
f = 100 kHz –105
f = 1 MHz –70
AC PERFORMANCE (continued)
Third-order harmonic distortion f = 10 kHz –139 dBc C
f = 100 kHz –122
f = 1 MHz -73
Second-order intermodulation distortion f = 1 MHz, 200-kHz Tone Spacing,
VOUT Envelope = 2 VPP
–70 dBc C
Third-order intermodulation distortion f = 1 MHz, 200-kHz Tone Spacing,
VOUT Envelope = 2 VPP
–83 dBc C
Signal-to-noise ratio, SNR f = 1 kHz, VOUT = 1 VRMS, 22-kHz bandwidth 0.00015% C
–116.4 dBc
Total harmonic distortion, THD f = 1 kHz, VOUT = 1 VRMS 0.00003% C
–130 dBc C
Input voltage noise f = 100 kHz 9.3 nV/√Hz C
Voltage noise 1/f corner frequency 147 Hz C
Input current noise f = 1 MHz 0.45 pA/√Hz C
Current noise 1/f corner frequency 14.7 kHz C
Overdrive recovery time, over/under Overdrive = 0.5 V 195/135 ns C
Closed-loop output impedance f = 100 kHz 0.028 Ω C
Channel to channel crosstalk (OPA2835) f = 10 kHz –120 dB C
DC PERFORMANCE
Open-loop voltage gain (AOL) 100 120 dB A
Input referred offset voltage TA = 25°C –500 ±100 500 µV A
TA = 0°C to 70°C –880 880 B
TA = –40°C to 85°C –1040 1040
TA = –40°C to 125°C –1850 1850
Input offset voltage drift(3) TA = 0°C to 70°C –8.5 ±1.4 8.5 µV/°C B
TA = –40°C to 85°C –9 ±1.5 9
TA = –40°C to 125°C –13.5 ±2.25 13.5
Input bias current(2) TA = 25°C 50 200 400 nA A
TA = 0°C to 70°C 47 410 B
TA = –40°C to 85°C 45 425
TA = –40°C to 125°C 45 530
Input bias current drift(3) TA = 0°C to 70°C –1.4 ±0.25 1.4 nA/°C B
TA = –40°C to 85°C –1.05 ±0.175 1.05
TA = –40°C to 125°C –1.1 ±0.185 1.1
Input offset current TA = 25°C –100 ±13 100 nA A
TA = 0°C to 70°C –100 ±13 100 B
TA = –40°C to 85°C –100 ±13 100
TA = –40°C to 125°C –100 ±13 100
Input offset current drift(3) TA = 0°C to 70°C –1.23 ±0.205 1.23 nA/°C B
TA = –40°C to 85°C –0.94 ±0.155 0.94
TA = –40°C to 125°C –0.94 ±0.155 0.94
INPUT
Common-mode input range low TA = 25°C, < 3-dB degradation in CMRR limit –0.2 0 V A
TA = –40°C to 125°C, < 3-dB degradation in CMRR limit –0.2 0 V B
Common-mode input range high TA = 25°C, < 3-dB degradation in CMRR limit 3.8 3.9 V A
TA = –40°C to 125°C, < 3-dB degradation in CMRR limit 3.8 3.9 V B
Common-mode rejection ratio 91 113 dB A
Input impedance common-mode 200 || 1.2 kΩ || pF C
Input impedance differential mode 200 || 1 kΩ || pF C
OUTPUT
Output voltage low TA = 25°C, G = 5 0.15 0.2 V A
TA = –40°C to 125°C, G = 5 0.15 0.2 V B
Output voltage high TA = 25°C, G = 5 4.75 4.8 V A
TA = –40°C to 125°C, G = 5 4.75 4.8 V B
Output saturation voltage, high/low TA = 25°C, G = 5 70/25 mV C
Output current drive TA = 25°C ±30 ±40 mA A
TA = –40°C to 125°C ±25 mA B
GAIN-SETTING RESISTORS (OPA835IRUN ONLY)
Resistor FB1 to FB2 DC resistance 2376 2400 2424 Ω A
Resistor FB2 to FB3 DC resistance 1782 1800 1818 Ω A
Resistor FB3 to FB4 DC resistance 594 600 606 Ω A
Resistor tolerance DC resistance –1% 1% A
Resistor temperature coefficient DC resistance <10 PPM C
POWER SUPPLY
Specified operating voltage 2.5 5.5 V B
Quiescent operating current per amplifier TA = 25°C 200 250 350 µA A
TA = –40°C to 125°C 150 365 µA B
Power supply rejection (±PSRR) 90 110 dB A
POWER DOWN (PIN MUST BE DRIVEN)
Enable voltage threshold Specified "on" above VS–+ 2.1 V 1.4 2.1 V A
Disable voltage threshold Specified "off" below VS–+ 0.7 V 0.7 1.4 V A
Power-down pin bias current PD = 0.5 V 20 500 nA A
Power-down quiescent current PD = 0.5 V 0.5 1.5 µA A
Turnon time delay Time from PD = high to VOUT = 90% of final value 200 ns C
Turnoff time delay Time from PD = low to VOUT = 10% of original value 60 ns C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) Current is considered positive out of the pin.
(3) Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range.

7.8 Typical Characteristics: VS = 2.7 V

Table 1. Table of Graphs

FIGURE TITLE FIGURE LOCATION
Small-Signal Frequency Response Figure 1
Large-Signal Frequency Response Figure 2
Noninverting Pulse Response Figure 3
Inverting Pulse Response Figure 4
Slew Rate vs Output Voltage Step Figure 5
Output Overdrive Recovery Figure 6
Harmonic Distortion vs Frequency Figure 7
Harmonic Distortion vs Load Resistance Figure 8
Harmonic Distortion vs Output Voltage Figure 9
Harmonic Distortion vs Gain Figure 10
Output Voltage Swing vs Load Resistance Figure 11
Output Saturation Voltage vs Load Current Figure 12
Output Impedance vs Frequency Figure 13
Frequency Response With Capacitive Load Figure 14
Series Output Resistor vs Capacitive Load Figure 15
Input Referred Noise vs Frequency Figure 16
Open-Loop Gain vs Frequency Figure 17
Common-Mode/Power Supply Rejection Ratios vs Frequency Figure 18
Crosstalk vs Frequency Figure 19
Power Down Response Figure 20
Input Offset Voltage Figure 21
Input Offset Voltage vs Free-Air Temperature Figure 22
Input Offset Voltage Drift Figure 23
Input Offset Current Figure 24
Input Offset Current vs Free-Air Temperature Figure 25
Input Offset Current Drift Figure 26
Test conditions unless otherwise noted: VS+ = +2.7 V, VS– = 0 V, VOUT = 1 Vpp, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, VIN_CM = mid-supply – 0.5 V. TA = 25°C
OPA835 OPA2835 tc1A_27V_los713.gif
Figure 1. Small-Signal Frequency Response
OPA835 OPA2835 tc5A_27V_los713.gif
Figure 3. Noninverting Pulse Response
OPA835 OPA2835 tc8A_27V_los713.gif
Figure 5. Slew Rate vs Output Voltage Step
OPA835 OPA2835 tcA15_27V_los713.gif
Figure 7. Harmonic Distortion vs Frequency
OPA835 OPA2835 tcA13_27V_los713.gif
Figure 9. Harmonic Distortion vs Output Voltage
OPA835 OPA2835 tc9A_27V_los713.gif
Figure 11. Output Voltage Swing vs Load Resistance
OPA835 OPA2835 tc11A_27V_los713.gif
Figure 13. Output Impedance vs Frequency
OPA835 OPA2835 tcA1_27V_los713.gif
Figure 15. Series Output Resistor vs Capacitive Load
OPA835 OPA2835 tcA11_27V_los713.gif
Figure 17. Open Loop Gain vs Frequency
OPA835 OPA2835 OPA2835IDGS_Xtalk_LOS713.gif
Figure 19. Crosstalk vs Frequency
OPA835 OPA2835 tcA3_27V_los713.gif
Figure 21. Input Offset Voltage
OPA835 OPA2835 tcA5_27V_los713.gif
Figure 23. Input Offset Voltage Drift
OPA835 OPA2835 tcA7_27V_los713.gif
Figure 25. Input Offset Current vs Free-Air Temperature
OPA835 OPA2835 tc2A_27V_los713.gif
Figure 2. Large-Signal Frequency Response
OPA835 OPA2835 tc6A_27V_los713.gif
Figure 4. Inverting Pulse Response
OPA835 OPA2835 tc7A_27V_los713.gif
Figure 6. Output Overdrive Recovery
OPA835 OPA2835 tcA14_27V_los713.gif
Figure 8. Harmonic Distortion vs Load Resistance
OPA835 OPA2835 tcA2_27V_los713.gif
Figure 10. Harmonic Distortion vs Gain
OPA835 OPA2835 tc10A_27V_los713.gif
Figure 12. Output Saturation Voltage vs Load Current
OPA835 OPA2835 tc3A_27V_los713.gif
Figure 14. Frequency Response With Capacitive Load
OPA835 OPA2835 2typchar_slos713.gif
Figure 16. Input Referred Noise vs Frequency
OPA835 OPA2835 tcA12_27V_los713.gif
Figure 18. Common-Mode/Power Supply Rejection Ratios vs Frequency
OPA835 OPA2835 tc12A_27V_los713.gif
Figure 20. Power Down Response
OPA835 OPA2835 tcA4_27V_los713.gif
Figure 22. Input Offset Voltage vs Free-Air Temperature
OPA835 OPA2835 tcA6_27V_los713.gif
Figure 24. Input Offset Current
OPA835 OPA2835 tcA8_27V_los713.gif
Figure 26. Input Offset Current Drift

7.9 Typical Characteristics: VS = 5 V

Table 2. Table of Graphs

FIGURE TITLE FIGURE LOCATION
Small-Signal Frequency Response Figure 27
Large-Signal Frequency Response Figure 28
Noninverting Pulse Response Figure 29
Inverting Pulse Response Figure 30
Slew Rate vs Output Voltage Step Figure 31
Output Overdrive Recovery Figure 32
Harmonic Distortion vs Frequency Figure 33
Harmonic Distortion vs Load Resistance Figure 34
Harmonic Distortion vs Output Voltage Figure 35
Harmonic Distortion vs Gain Figure 36
Output Voltage Swing vs Load Resistance Figure 37
Output Saturation Voltage vs Load Current Figure 38
Output Impedance vs Frequency Figure 39
Frequency Response With Capacitive Load Figure 40
Series Output Resistor vs Capacitive Load Figure 41
Input Referred Noise vs Frequency Figure 42
Open Loop Gain vs Frequency Figure 43
Common-Mode/Power Supply Rejection Ratios vs Frequency Figure 44
Crosstalk vs Frequency Figure 45
Power Down Response Figure 46
Input Offset Voltage Figure 47
Input Offset Voltage vs Free-Air Temperature Figure 48
Input Offset Voltage Drift Figure 49
Input Offset Current Figure 50
Input Offset Current vs Free-Air Temperature Figure 51
Input Offset Current Drift Figure 52
Test conditions unless otherwise noted: VS+ = +5 V, VS– = 0 V, VOUT = 2 Vpp, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply. TA = 25°C
OPA835 OPA2835 tc1_5V_los713.gif
Figure 27. Small-Signal Frequency Response
OPA835 OPA2835 tc5_5V_los713.gif
Figure 29. Noninverting Pulse Response
OPA835 OPA2835 tc8_5V_los713.gif
Figure 31. Slew Rate vs Output Voltage Step
OPA835 OPA2835 tcB13_5V_los713.gif
Figure 33. Harmonic Distortion vs Frequency
OPA835 OPA2835 tcB14_5V_los713.gif
Figure 35. Harmonic Distortion vs Output Voltage
OPA835 OPA2835 tc9_5V_los713.gif
Figure 37. Output Voltage Swing vs Load Resistance
OPA835 OPA2835 tc11_5V_los713.gif
Figure 39. Output Impedance vs Frequency
OPA835 OPA2835 tcB1_5V_los713.gif
Figure 41. Series Output Resistor vs Capacitive Load
OPA835 OPA2835 tcB11_5V_los713.gif
Figure 43. Open-Loop Gain vs Frequency
OPA835 OPA2835 OPA2835IDGS_Xtalk_LOS713.gif
Figure 45. Crosstalk vs Frequency
OPA835 OPA2835 tcB3_5V_los713.gif
Figure 47. Input Offset Voltage
OPA835 OPA2835 tcB4_5V_los713.gif
Figure 49. Input Offset Voltage Drift
OPA835 OPA2835 tcB7_5V_los713.gif
Figure 51. Input Offset Current vs Free-Air Temperature
OPA835 OPA2835 tc2_5V_los713.gif
Figure 28. Large-Signal Frequency Response
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Figure 30. Inverting Pulse Response
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Figure 32. Output Overdrive Recovery
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Figure 34. Harmonic Distortion vs Load Resistance
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Figure 36. Harmonic Distortion vs Gain
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Figure 38. Output Saturation Voltage vs Load Current
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Figure 40. Frequency Response With Capacitive Load
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Figure 42. Input Referred Noise vs Frequency
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Figure 44. Common-Mode/Power Supply Rejection Ratios vs Frequency
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Figure 46. Power Down Response
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Figure 48. Input Offset Voltage vs Free-Air Temperature
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Figure 50. Input Offset Current
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Figure 52. Input Offset Current Drift