SBOS630D December   2013  – August 2016 OPA857

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Transimpedance Amplifier (TIA) Block
      2. 7.3.2 Reference Voltage (REF) Block
      3. 7.3.3 Integrated Test Structure (TEST) Block
      4. 7.3.4 Internal Clamping Circuit (CLAMP) Block
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gain Control
      2. 7.4.2 Test Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 TIA With Associated Signal Chain
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Extending Transimpedance Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
        2. 11.1.1.2 Spice Model
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGT Package
16-Pin VQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CTRL 2 I Control pin for transimpedance gain.
GND, logic 0 = 5-kΩ internal resistance; +VS, logic 1 = 20-kΩ internal resistance.
GND 1, 3, 4, 6, 7, 12 I Ground
IN 15 I Input
NC 16 — Not connected
OUT 8 O Signal output
OUTN 5 O Common-mode voltage output reference
Test_IN 14 I Test mode input. Connect to +VS during normal operation.
Test_SD 13 I Test mode enable. Connect to GND for normal operation, and connect to +VS to enable test mode.
+VS 9, 10, 11 I Supply voltage