JAJSHS5C August   2019  – August 2020 OPA862

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = ±2.5 V to ±5 V
    6. 6.6 Typical Characteristics: VS = ±5 V
    7. 6.7 Typical Characteristics: VS = ±2.5 V
    8. 6.8 Typical Characteristics: VS = 1.9 V, –1.4 V
    9. 6.9 Typical Characteristics: VS = 1.9 V, –1.4 V to ±5 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and ESD Protection
      2. 7.3.2 Anti-Phase Reversal Protection
      3. 7.3.3 Precision and Low Noise
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±1.5 V to ±6.3 V)
      2. 7.4.2 Single-Supply Operation (3 V to 12.6 V)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single-Ended-to-Differential Gain of 4 V/V
    2. 8.2 Typical Applications
      1. 8.2.1 Single-Ended to Differential with 2.5-V Output Common-Mode Voltage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transimpedance Amplifier Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 DC Level-Shifting
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.3 DC Level-Shifting

Often, applications must level-shift a ground-referenced signal to a non-ground voltage. Configurations in Figure 8-10 and Figure 8-11 show two different ways of level-shifting a signal by using the OPA862 without having to use external resistors, saving board cost and space. These configurations leverage the fixed noninverting gain-of-2 configuration of A2 and the summing configuration of A1 to level-shift the signal at VOUT–. The internal resistors of the OPA862 are extremely well-matched to maintain the gain-of-2 accuracy of A2. Similarly matched external resistors can add significant cost to the system and often are more expensive than the amplifier itself.

Apart from the polarity of the VDC-shift at the output, a key difference between the configurations of Figure 8-10 and Figure 8-11 is that in the case of Figure 8-10, VDC only must be capable of driving the IB of A1 but in the case of Figure 8-11, VDC must be capable of driving higher currents, as given by I = VDC / RG when a noninverting input of A1 is grounded.

GUID-E9927545-2C8A-4B1C-96E5-EA2CCABDB98E-low.gifFigure 8-10 Level-Shifting With a DC Source of Polarity Opposite to the Desired DC Shift
GUID-59BB90E0-AB14-49D0-BC46-33712E951643-low.gifFigure 8-11 Level-Shifting With a DC Source of Polarity Same as the Desired DC Shift