JAJSGF2C August   2012  – October 2018 PCM5121 , PCM5122

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      単純化したシステム図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
    1. 7.0.1 RHB Package I2C Mode (MODE1 tied to DGND and MODE2 tied to DVDD) Top View
    2. 7.0.2 RHB Package SPI Mode (MODE1 tied to DVDD) Top View
    3. 7.0.3 RHB Package Hardwired Mode (MODE1 tied to DGND, MODE2 tied to DGND) Top View
    4.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements: SCK Input
    7. 8.7 Timing Requirements: XSMT
    8. 8.8 Switching Characteristics
    9. 8.9 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Terminology
      2. 9.3.2 Audio Data Interface
        1. 9.3.2.1 Audio Serial Interface
        2. 9.3.2.2 PCM Audio Data Formats
        3. 9.3.2.3 Zero Data Detect
      3. 9.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 9.3.4 Audio Processing
        1. 9.3.4.1 PCM512x Audio Processing
          1. 9.3.4.1.1 Overview
          2. 9.3.4.1.2 Software
        2. 9.3.4.2 Interpolation Filter
        3. 9.3.4.3 Fixed Audio Processing Flow (Program 5)
          1. 9.3.4.3.1 Filter Programming Changes
          2. 9.3.4.3.2 Processing Blocks – Detailed Descriptions
          3. 9.3.4.3.3 Biquad Section
          4. 9.3.4.3.4 Dynamic Range Compression
          5. 9.3.4.3.5 Stereo Mixer
          6. 9.3.4.3.6 Stereo Multiplexer
          7. 9.3.4.3.7 Mono Mixer
          8. 9.3.4.3.8 Master Volume Control
          9. 9.3.4.3.9 Miscellaneous Coefficients
      5. 9.3.5 DAC Outputs
        1. 9.3.5.1 Analog Outputs
        2. 9.3.5.2 Recommended Output Filter for the PCM512x
        3. 9.3.5.3 Choosing Between VREF and VCOM Modes
          1. 9.3.5.3.1 Voltage Reference and Output Levels
          2. 9.3.5.3.2 Mode Switching Sequence, from VREF Mode to VCOM Mode
        4. 9.3.5.4 Digital Volume Control
          1. 9.3.5.4.1 Emergency Ramp-Down
        5. 9.3.5.5 Analog Gain Control
      6. 9.3.6 Reset and System Clock Functions
        1. 9.3.6.1 Clocking Overview
        2. 9.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
        3. 9.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
        4. 9.3.6.4 Clock Generation Using the PLL
        5. 9.3.6.5 PLL Calculation
          1. 9.3.6.5.1 Examples:
            1. 9.3.6.5.1.1 Recommended PLL Settings
        6. 9.3.6.6 Clock Master Mode from Audio Rate Master Clock
        7. 9.3.6.7 Clock Master from a Non-Audio Rate Master Clock
    4. 9.4 Device Functional Modes
      1. 9.4.1 Choosing a Control Mode
        1. 9.4.1.1 Software Control
          1. 9.4.1.1.1 SPI Interface
            1. 9.4.1.1.1.1 Register Read and Write Operation
          2. 9.4.1.1.2 I2C Interface
            1. 9.4.1.1.2.1 Slave Address
            2. 9.4.1.1.2.2 Register Address Auto-Increment Mode
            3. 9.4.1.1.2.3 Packet Protocol
            4. 9.4.1.1.2.4 Write Register
            5. 9.4.1.1.2.5 Read Register
            6. 9.4.1.1.2.6 Timing Characteristics
      2. 9.4.2 VREF and VCOM Modes
    5. 9.5 Programming
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Distribution and Requirements
    2. 11.2 Recommended Powerdown Sequence
      1. 11.2.1 XSMT = 0
      2. 11.2.2 Clock Error Detect
      3. 11.2.3 Planned Shutdown
      4. 11.2.4 Unplanned Shutdown
    3. 11.3 External Power Sense Undervoltage Protection Mode
    4. 11.4 Power-On Reset Function
      1. 11.4.1 Power-On Reset, DVDD 3.3-V Supply
      2. 11.4.2 Power-On Reset, DVDD 1.8-V Supply
    5. 11.5 PCM512x Power Modes
      1. 11.5.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 11.5.2 Power Save Modes
      3. 11.5.3 Power Save Parameter Programming
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Register Maps
    1. 13.1 PCM512x Register Map
      1. 13.1.1 Detailed Register Descriptions
        1. 13.1.1.1 Register Map Summary
        2. 13.1.1.2 Page 0 Registers
        3. 13.1.1.3 Page 1 Registers
        4. 13.1.1.4 Page 44 Registers
        5. 13.1.1.5 Page 253 Registers
      2. 13.1.2 PLL Tables for Software Controlled Devices
      3. 13.1.3 Coefficient Data Formats
      4. 13.1.4 Power Down and Reset Behavior
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 開発サポート
    2. 14.2 ドキュメントのサポート
    3. 14.3 関連リンク
    4. 14.4 ドキュメントの更新通知を受け取る方法
    5. 14.5 コミュニティ・リソース
    6. 14.6 商標
    7. 14.7 静電気放電に関する注意事項
    8. 14.8 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

13.1 PCM512x Register Map

In any page, register 0 is the Page Select Register. The register value selects the Register Page from 0 to 255 for next read or write command.

Table 49. Register Map Overview

REGISTER NUMBER DESCRIPTION
Page 0
0 Page select register
1 Analog control register
2 Standby, Powerdown requests
3 Mute
4 PLL Lock Flag, PLL enable
5 Reserved
6 SPI MISO function select
7 De-emphasis enable, SDOUT select
8 GPIO enables
9 BCK, LRCLK configuration
10 DSP GPIO Input
11 Reserved
12 Master mode BCK, LRCLK reset
13 PLL clock source select
14 - 19 Reserved
20 - 24 PLL dividers
25, 26 Reserved
27 DSP clock divider
28 DAC clock divider
29 NCP clock divider
30 OSR clock divider
31 Reserved
32, 33 Master mode dividers
34 fS speed mode
35, 36 IDAC (number of DSP clock cycles available in one audio frame)
37 Ignore various errors
38,39 Reserved
40, 41 I2S configuration
42 DAC data path
43 DSP program selection
44 Clock missing detection period
59 Auto mute time
60 - 64 Digital volume
65 Auto mute
75 - 79 Reserved
80 - 85 GPIOn output selection
86, 87 GPIO control
88, 89 Reserved
90 DSP overflow
91 - 94 Sample rate status
95 - 107 Reserved
108 Analog mute monitor
109 - 118 Reserved
119 GPIO input
120 Auto Mute flags
121 Reserved
Page 1
1 Output amplitude type
2 Analog gain control
3, 4 Reserved
5 Undervoltage protection
6 Analog mute control
7 Analog gain boost
8, 9 VCOM configuration
Page 44
1 Coefficient memory (CRAM) control
Pages 44 - 52 Coefficient buffer - A (256 coeffs x 24 bits) : See Table 51
Pages 62 - 70 Coefficient buffer - B (256 coeffs x 24 bits) : See Table 52
71 - 252 Reserved
Page 253
63, 64 Clock Flex Mode
Pages 254 - 255 Reserved

The PCM512x has a register map split into multiple pages. Pages 0 and 1 control of the DAC and other on-chip peripherals. Pages 44 through 52 are used for Coefficient A memory, while Pages 62-70 are coefficient B memory. Pages 152-186 contain the miniDSP instruction memory. Page 253 is where the Clock Flex Mode register is located.

Table 50. PCM512x Register Page Structure

Page: 0 1 2-43 44-52 53-61 62-70 71-252 253 254-255
Func: Control Analog Control Reserved Coeffient A Reserved Coeffient B Reserved Clock Flex Reserved
Desc: General Control and Configuration Analog Control 256 24-bit coefficients,
30 coefficients per page,
4 registers per coefficient		 256 24-bit coefficients,
30 coefficients per page,
4 registers per coefficient		 Clock Flex Mode

Table 51. Coefficient Buffer-A Map

COEFF NO PAGE NO BASE REGISTER BASE REGISTER + 0 BASE REGISTER + 1 BASE REGISTER + 2 BASE REGISTER + 3
C0 44 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C1 44 12 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C29 44 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C30 45 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C59 45 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C60 46 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C89 46 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C90 47 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C119 47 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C120 48 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C149 48 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C150 49 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C179 49 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C180 50 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C209 50 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C210 51 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C239 51 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C240 52 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C255 52 68 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.

Table 52. Coefficient Buffer-B Map

COEFF NO PAGE NO BASE REGISTER BASE REGISTER + 0 BASE REGISTER + 1 BASE REGISTER + 2 BASE REGISTER + 3
C0 62 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C1 62 12 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C29 62 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C30 63 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C59 63 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C60 64 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C89 64 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C90 65 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C119 65 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C120 66 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C149 66 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C150 67 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C179 67 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C180 68 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C209 68 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C210 69 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C239 69 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C240 70 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C255 70 68 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.