JAJSGF2C August 2012 – October 2018 PCM5121 , PCM5122
PRODUCTION DATA.
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 1 | 01 | RSV | RSV | RSV | RSTM | RSV | RSV | RSV | RSTR |
| Reset Value | 0 | 0 | |||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| RSTM | Reset Modules | ||||||||
| This bit resets the interpolation filter and the DAC modules. Since the DSP is also reset, the coeffient RAM content will also be cleared by the DSP. This bit is auto cleared and can be set only in standby mode. | |||||||||
| Default value: 0 | |||||||||
| 0: Normal | |||||||||
| 1: Reset modules | |||||||||
| RSTR | Reset Registers | ||||||||
| This bit resets the mode registers back to their initial values. The RAM content is not cleared, but the execution source will be back to ROM. This bit is auto cleared and must be set only when the DAC is in standby mode (resetting registers when the DAC is running is prohibited and not supported). | |||||||||
| Default value: 0 | |||||||||
| 0: Normal | |||||||||
| 1: Reset mode registers | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 2 | 02 | RSV | RSV | RSV | RQST | RSV | RSV | RSV | RQPD |
| Reset Value | 0 | 0 | |||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| RQST | Standby Request | ||||||||
| When this bit is set, the DAC will be forced into a system standby mode, which is also the mode the system enters in the case of clock errors. In this mode, most subsystems will be powered down but the charge pump and digital power supply. | |||||||||
| Default value: 0 | |||||||||
| 0: Normal operation | |||||||||
| 1: Standby mode | |||||||||
| RQPD | Powerdown Request | ||||||||
| When this bit is set, the DAC will be forced into powerdown mode, in which the power consumption would be minimum as the charge pump is also powered down. However, it will take longer to restart from this mode. This mode has higher precedence than the standby mode, that is, setting this bit along with bit 4 for standby mode will result in the DAC going into powerdown mode. | |||||||||
| Default value: 0 | |||||||||
| 0: Normal operation | |||||||||
| 1: Powerdown mode | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 3 | 03 | RSV | RSV | RSV | RQML | RSV | RSV | RSV | RQMR |
| Reset Value | 0 | 0 | |||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| RQML | Mute Left Channel | ||||||||
| This bit issues soft mute request for the left channel. The volume will be smoothly ramped down/up to avoid pop/click noise. | |||||||||
| Default value: 0 | |||||||||
| 0: Normal volume | |||||||||
| 1: Mute | |||||||||
| RQMR | Mute Right Channel | ||||||||
| This bit issues soft mute request for the right channel. The volume will be smoothly ramped down/up to avoid pop/click noise. | |||||||||
| Default value: 0 | |||||||||
| 0: Normal volume | |||||||||
| 1: Mute | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 4 | 04 | RSV | RSV | RSV | PLCK | RSV | RSV | RSV | PLLE |
| Reset Value | 1 | ||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| PLCK | PLL Lock Flag (Read Only) | ||||||||
| This bit indicates whether the PLL is locked or not. When the PLL is disabled this bit always shows that the PLL is not locked. | |||||||||
| 0: The PLL is locked | |||||||||
| 1: The PLL is not locked | |||||||||
| PLLE | PLL Enable | ||||||||
| This bit enables or disables the internal PLL. When PLL is disabled, the master clock will be switched to the SCK. | |||||||||
| Default value: 1 | |||||||||
| 0: Disable PLL | |||||||||
| 1: Enable PLL | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 6 | 06 | RSV | RSV | RSV | RSV | RSV | RSV | FSMI1 | FSMI0 |
| Reset Value | 0 | 0 | |||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| FSMI[1:0] | SPI MISO function sel | ||||||||
| These bits select the function of the SPI_MISO pin when in SPI mode. If the pin is set as GPIO, register readout via SPI is not possible. | |||||||||
| Default value: 00 | |||||||||
| 00: SPI_MISO | |||||||||
| 01: GPIO1 | |||||||||
| Others: Reserved (Do not set) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 7 | 07 | RSV | RSV | RSV | DEMP | RSV | RSV | RSV | SDSL |
| Reset Value | 0 | 0 | |||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| DEMP | De-Emphasis Enable | ||||||||
| This bit enables or disables the de-emphasis filter. The default coefficients are for 44.1kHz sampling rate, but can be changed by reprogramming the appropriate coeffients in RAM. | |||||||||
| Default value: 0 | |||||||||
| 0: De-emphasis filter is disabled | |||||||||
| 1: De-emphasis filter is enabled | |||||||||
| SDSL | SDOUT Select | ||||||||
| This bit selects what is being output as SDOUT via GPIO pins. | |||||||||
| Default value: 0 | |||||||||
| 0: SDOUT is the DSP output (post-processing) | |||||||||
| 1: SDOUT is the DSP input (pre-processing) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 8 | 08 | RSV | RSV | G6OE | G5OE | G4OE | G3OE | G2OE | G1OE |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | |||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| G6OE | GPIO6 Output Enable | ||||||||
| This bit sets the direction of the GPIO6 pin | |||||||||
| Default value: 0 | |||||||||
| 0: GPIO6 is input | |||||||||
| 1: GPIO6 is output | |||||||||
| G5OE | GPIO5 Output Enable | ||||||||
| This bit sets the direction of the GPIO5 pin | |||||||||
| Default value: 0 | |||||||||
| 0: GPIO5 is input | |||||||||
| 1: GPIO5 is output | |||||||||
| G4OE | GPIO4 Output Enable | ||||||||
| This bit sets the direction of the GPIO4 pin | |||||||||
| Default value: 0 | |||||||||
| 0: GPIO4 is input | |||||||||
| 1: GPIO4 is output | |||||||||
| G3OE | GPIO3 Output Enable | ||||||||
| This bit sets the direction of the GPIO3 pin | |||||||||
| Default value: 0 | |||||||||
| 0: GPIO3 is input | |||||||||
| 1: GPIO3 is output | |||||||||
| G2OE | GPIO2 Output Enable | ||||||||
| This bit sets the direction of the GPIO2 pin | |||||||||
| Default value: 0 | |||||||||
| 0: GPIO2 is input | |||||||||
| 1: GPIO2 is output | |||||||||
| G1OE | GPIO1 Output Enable | ||||||||
| This bit sets the direction of the GPIO1 pin | |||||||||
| Default value: 0 | |||||||||
| 0: GPIO1 is input | |||||||||
| 1: GPIO1 is output | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 9 | 09 | RSV | RSV | BCKP | BCKO | RSV | RSV | RSV | LRKO |
| Reset Value | 0 | 0 | 0 | ||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| BCKP | BCK Polarity | ||||||||
| This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the LRCK and DIN edges are aligned to the rising edge of the BCK. Normally they are assumed to be aligned to the falling edge of the BCK. | |||||||||
| Default value: 0 | |||||||||
| 0: Normal BCK mode | |||||||||
| 1: Inverted BCK mode | |||||||||
| BCKO | BCK Output Enable | ||||||||
| This bit sets the BCK pin direction to output for I2S master mode operation. In I2S master mode the PCM5xxx outputs the reference BCK and LRCK, and the external source device provides the DIN according to these clocks. Use Page 0 / Register 32 to program the division factor of the SCK to yield the desired BCK rate (normally 64FS) | |||||||||
| Default value: 0 | |||||||||
| 0: BCK is input (I2S slave mode) | |||||||||
| 1: BCK is output (I2S master mode) | |||||||||
| LRKO | LRCLK Output Enable | ||||||||
| This bit sets the LRCK pin direction to output for I2S master mode operation. In I2S master mode the PCM5xxx outputs the reference BCK and LRCK, and the external source device provides the DIN according to these clocks. Use Page 0 / Register 33 to program the division factor of the BCK to yield 1FS for LRCK. | |||||||||
| Default value: 0 | |||||||||
| 0: LRCK is input (I2S slave mode) | |||||||||
| 1: LRCK is output (I2S master mode) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 10 | 0A | DSPG7 | DSPG6 | DSPG5 | DSPG4 | DSPG3 | DSPG2 | DSPG1 | DSPG0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| DSPG[7:0] | DSP GPIO Input | ||||||||
| The DSP accepts a 24-bit external control signals input. The value set in this register will go to bit 16:8 of this external input. | |||||||||
| Default value: 00000000 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 12 | 0C | RSV | RSV | RSV | RSV | RSV | RSV | RBCK | RLRK |
| Reset Value | 0 | 0 | |||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| RBCK | Master Mode BCK Divider Reset | ||||||||
| This bit, when set to 0, will reset the SCK divider to generate BCK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly. | |||||||||
| Default value: 0 | |||||||||
| 0: Master mode BCK clock divider is reset | |||||||||
| 1: Master mode BCK clock divider is functional | |||||||||
| RLRK | Master Mode LRCK Divider Reset | ||||||||
| This bit, when set to 0, will reset the BCK divider to generate LRCK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly. | |||||||||
| Default value: 0 | |||||||||
| 0: Master mode LRCK clock divider is reset | |||||||||
| 1: Master mode LRCK clock divider is functional | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 13 | 0D | RSV | SREF2 | SREF1 | SREF0 | RSV | RSV | RSV | RSV |
| Reset Value | 0 | 0 | 0 | ||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| SREF[2:0] | PLL Reference | ||||||||
| This bit select the source clock for internal PLL. This bit is ignored and overriden in clock auto set mode. | |||||||||
| Default value: 000 | |||||||||
| 000: The PLL reference clock is SCK | |||||||||
| 001: The PLL reference clock is BCK | |||||||||
| 010: Reserved | |||||||||
| 011: The PLL reference clock is GPIO (selected using Page 0 / Register 18) | |||||||||
| others: Reserved (PLL reference is muted) | |||||||||
| SREF | PLL Reference | ||||||||
| Default value: 0 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 14 | 0E | RSV | SDAC2 | SDAC1 | SDAC0 | RSV | RSV | RSV | RSV |
| Reset Value | 0 | 0 | 0 | ||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| SDAC[2:0] | DAC clock source | ||||||||
| These bits select the source clock for DAC clock divider. | |||||||||
| Default value: 000 | |||||||||
| This Register requires use of the Clock Flex Register | |||||||||
| 000: Master clock (PLL/SCK and OSC auto-select) | |||||||||
| 001: PLL clock | |||||||||
| 010: Reserved | |||||||||
| 011: SCK clock | |||||||||
| 100: BCK clock | |||||||||
| others: Reserved (muted) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 18 | 12 | RSV | RSV | RSV | RSV | RSV | GREF2 | GREF1 | GREF0 |
| Reset Value | 0 | 0 | 0 | ||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| GREF[2:0] | GPIO Source for PLL reference clk | ||||||||
| These bits select the GPIO pins as clock input source when GPIO is selected as the PLL reference clock source. | |||||||||
| Default value: 000 | |||||||||
| This register requires use of the Clock Flex Register.000: GPIO1 | |||||||||
| 001: GPIO2 | |||||||||
| 010: GPIO3 | |||||||||
| 011: GPIO4 | |||||||||
| 100: GPIO5 | |||||||||
| 101: GPIO6 | |||||||||
| others: Reserved (muted) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 19 | 13 | RSV | RSV | RSV | RSV | RSV | RSV | RSV | RQSY |
| Reset Value | 0 | ||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| RQSY | Sync request | ||||||||
| This bit, when set to 1 will issue the clock resynchronization by synchronously resets the DAC, CP and OSR clocks. The actual clock resynchronization takes place when this bit is set back to 0, where the DAC, CP and OSR clocks are resumed at the beginning of the audio frame. | |||||||||
| Default value: 0 | |||||||||
| 0: Resume DAC, CP and OSR clocks synchronized to the beginning of audio frame | |||||||||
| 1: Halt DAC, CP and OSR clocks as the beginning of resynchronization process | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 20 | 14 | RSV | RSV | RSV | RSV | PPDV3 | PPDV2 | PPDV1 | PPDV0 |
| Reset Value | 0 | 0 | 0 | 0 | |||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| PPDV[3:0] | PLL P | ||||||||
| These bits set the PLL divider P factor. These bits are ignored in clock auto set mode. | |||||||||
| Default value: 0000 | |||||||||
| 0000: P=1 | |||||||||
| 0001: P=2 | |||||||||
| ... | |||||||||
| 1110: P=15 | |||||||||
| 1111: Prohibited (do not set this value) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 21 | 15 | RSV | RSV | PJDV5 | PJDV4 | PJDV3 | PJDV2 | PJDV1 | PJDV0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | |||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| PJDV[5:0] | PLL J | ||||||||
| These bits set the J part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. | |||||||||
| Default value: 000000 | |||||||||
| 000000: Prohibited (do not set this value) | |||||||||
| 000001: J=1 | |||||||||
| 000010: J=2 | |||||||||
| ... | |||||||||
| 111111: J=63 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 22 | 16 | RSV | RSV | PDDV13 | PDDV12 | PDDV11 | PDDV10 | PDDV9 | PDDV8 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
| 23 | 17 | PDDV7 | PDDV6 | PDDV5 | PDDV4 | PDDV3 | PDDV2 | PDDV1 | PDDV0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| PDDV[13:0] | PLL D (MSB) | ||||||||
| These bits set the D part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. | |||||||||
| Default value: 00000000000000 | |||||||||
| 0 (in decimal): D=0000 | |||||||||
| 1 (in decimal): D=0001 | |||||||||
| ... | |||||||||
| 9999 (in decimal): D=9999 | |||||||||
| others: Prohibited (do not set) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 24 | 18 | RSV | RSV | RSV | RSV | PRDV3 | PRDV2 | PRDV1 | PRDV0 |
| Reset Value | 0 | 0 | 0 | 0 | |||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| PRDV[3:0] | PLL R | ||||||||
| These bits set the R part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. | |||||||||
| Default value: 0000 | |||||||||
| 0000: R=1 | |||||||||
| 0001: R=2 | |||||||||
| ... | |||||||||
| 1111: R=16 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 27 | 1B | RSV | DDSP6 | DDSP5 | DDSP4 | DDSP3 | DDSP2 | DDSP1 | DDSP0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| DDSP[6:0] | DSP Clock Divider | ||||||||
| These bits set the source clock divider value for the DSP clock. These bits are ignored in clock auto set mode. | |||||||||
| Default value: 0000000 | |||||||||
| 0000000: Divide by 1 | |||||||||
| 0000001: Divide by 2 | |||||||||
| ... | |||||||||
| 1111111: Divide by 128 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 28 | 1C | RSV | DDAC6 | DDAC5 | DDAC4 | DDAC3 | DDAC2 | DDAC1 | DDAC0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| DDAC[6:0] | DAC Clock Divider | ||||||||
| These bits set the source clock divider value for the DAC clock. These bits are ignored in clock auto set mode. | |||||||||
| Default value: 0000000 | |||||||||
| 0000000: Divide by 1 | |||||||||
| 0000001: Divide by 2 | |||||||||
| ... | |||||||||
| 1111111: Divide by 128 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 29 | 1D | RSV | DNCP6 | DNCP5 | DNCP4 | DNCP3 | DNCP2 | DNCP1 | DNCP0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| DNCP[6:0] | NCP Clock Divider | ||||||||
| These bits set the source clock divider value for the CP clock. These bits are ignored in clock auto set mode. | |||||||||
| Default value: 0000000 | |||||||||
| 0000000: Divide by 1 | |||||||||
| 0000001: Divide by 2 | |||||||||
| ... | |||||||||
| 1111111: Divide by 128 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 30 | 1E | RSV | DOSR6 | DOSR5 | DOSR4 | DOSR3 | DOSR2 | DOSR1 | DOSR0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| DOSR[6:0] | OSR Clock Divider | ||||||||
| These bits set the source clock divider value for the OSR clock. These bits are ignored in clock auto set mode. | |||||||||
| Default value: 0000000 | |||||||||
| 0000000: Divide by 1 | |||||||||
| 0000001: Divide by 2 | |||||||||
| ... | |||||||||
| 1111111: Divide by 128 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 32 | 20 | RSV | DBCK6 | DBCK5 | DBCK4 | DBCK3 | DBCK2 | DBCK1 | DBCK0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| DBCK[6:0] | Master Mode BCK Divider | ||||||||
| These bits set the SCK divider value to generate I2S master BCK clock. | |||||||||
| Default value: 0000000 | |||||||||
| 0000000: Divide by 1 | |||||||||
| 0000001: Divide by 2 | |||||||||
| ... | |||||||||
| 1111111: Divide by 128 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 33 | 21 | DLRK7 | DLRK6 | DLRK5 | DLRK4 | DLRK3 | DLRK2 | DLRK1 | DLRK0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| DLRK[7:0] | Master Mode LRCK Divider | ||||||||
| These bits set the I2S master BCK clock divider value to generate I2S master LRCK clock. | |||||||||
| Default value: 00000000 | |||||||||
| 00000000: Divide by 1 | |||||||||
| 00000001: Divide by 2 | |||||||||
| ... | |||||||||
| 11111111: Divide by 256 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 34 | 22 | RSV | RSV | RSV | I16E | RSV | RSV | FSSP1 | FSSP0 |
| Reset Value | 0 | 0 | 0 | ||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| I16E | 16x Interpolation | ||||||||
| This bit enables or disables the 16x interpolation mode | |||||||||
| Default value: 0 | |||||||||
| 0: 8x interpolation | |||||||||
| 1: 16x interpolation | |||||||||
| FSSP[1:0] | FS Speed Mode | ||||||||
| These bits select the FS operation mode, which must be set according to the current audio sampling rate. These bits are ignored in clock auto set mode. | |||||||||
| Default value: 00 | |||||||||
| 00: Single speed (FS ≤ 48 kHz) | |||||||||
| 01: Double speed (48 kHz < FS ≤ 96 kHz) | |||||||||
| 10: Quad speed (96 kHz < FS ≤ 192 kHz) | |||||||||
| 11: Octal speed (192 kHz < FS ≤ 384 kHz) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 35 | 23 | IDAC15 | IDAC14 | IDAC13 | IDAC12 | IDAC11 | IDAC10 | IDAC9 | IDAC8 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 36 | 24 | IDAC7 | IDAC6 | IDAC5 | IDAC4 | IDAC3 | IDAC2 | IDAC1 | IDAC0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| IDAC[15:0] | IDAC (MSB) | ||||||||
| These bits specify the number of DSP clock cycles available in one audio frame. The value should match the DSP clock FS ratio. These bits are ignored in clock auto set mode. | |||||||||
| Default value: 0000000100000000 | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 37 | 25 | RSV | IDFS | IDBK | IDSK | IDCH | IDCM | DCAS | IPLK |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| IDFS | Ignore FS Detection | ||||||||
| This bit controls whether to ignore the FS detection. When ignored, FS error will not cause a clock error. | |||||||||
| Default value: 0 | |||||||||
| 0: Regard FS detection | |||||||||
| 1: Ignore FS detection | |||||||||
| IDBK | Ignore BCK Detection | ||||||||
| This bit controls whether to ignore the BCK detection against LRCK. The BCK must be stable between 32FS and 256FS inclusive or an error will be reported. When ignored, a BCK error will not cause a clock error. | |||||||||
| Default value: 0 | |||||||||
| 0: Regard BCK detection | |||||||||
| 1: Ignore BCK detection | |||||||||
| IDSK | Ignore SCK Detection | ||||||||
| This bit controls whether to ignore the SCK detection against LRCK. Only some certain SCK ratios within some error margin are allowed. When ignored, an SCK error will not cause a clock error. | |||||||||
| Default value: 0 | |||||||||
| 0: Regard SCK detection | |||||||||
| 1: Ignore SCK detection | |||||||||
| IDCH | Ignore Clock Halt Detection | ||||||||
| This bit controls whether to ignore the SCK halt (static or frequency is lower than acceptable) detection. When ignored an SCK halt will not cause a clock error. | |||||||||
| Default value: 0 | |||||||||
| 0: Regard SCK halt detection | |||||||||
| 1: Ignore SCK halt detection | |||||||||
| IDCM | Ignore LRCK/BCK Missing Detection | ||||||||
| This bit controls whether to ignore the LRCK/BCK missing detection. The LRCK/BCK need to be in low state (not only static) to be deemed missing. When ignored an LRCK/BCK missing will not cause the DAC go into powerdown mode. | |||||||||
| Default value: 0 | |||||||||
| 0: Regard LRCK/BCK missing detection | |||||||||
| 1: Ignore LRCK/BCK missing detection | |||||||||
| DCAS | Disable Clock Divider Autoset | ||||||||
| This bit enables or disables the clock auto set mode. When dealing with uncommon audio clock configuration, the auto set mode must be disabled and all clock dividers must be set manually. Addtionally, some clock detectors might also need to be disabled. The clock autoset feature will not work with PLL enabled in VCOM mode. In this case this feature has to be disabled and the clock dividers must be set manually. | |||||||||
| Default value: 0 | |||||||||
| 0: Enable clock auto set | |||||||||
| 1: Disable clock auto set | |||||||||
| IPLK | Ignore PLL Lock Detection | ||||||||
| This bit controls whether to ignore the PLL lock detection. When ignored, PLL unlocks will not cause a clock error. The PLL lock flag at Page 0 / Register 4, bit 4 is always correct regardless of this bit. | |||||||||
| Default value: 0 | |||||||||
| 0: PLL unlocks raise clock error | |||||||||
| 1: PLL unlocks are ignored | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 40 | 28 | RSV | RSV | AFMT1 | AFMT0 | RSV | RSV | ALEN1 | ALEN0 |
| Reset Value | 0 | 0 | 1 | 0 | |||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| AFMT[1:0] | I2S Data Format | ||||||||
| These bits control both input and output audio interface formats for DAC operation. | |||||||||
| Default value: 00 | |||||||||
| 00: I2S | |||||||||
| 01: TDM/DSP | |||||||||
| 10: RTJ | |||||||||
| 11: LTJ | |||||||||
| ALEN[1:0] | I2S Word Length | ||||||||
| These bits control both input and output audio interface sample word lengths for DAC operation. | |||||||||
| Default value: 10 | |||||||||
| 00: 16 bits | |||||||||
| 01: 20 bits | |||||||||
| 10: 24 bits | |||||||||
| 11: 32 bits | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 41 | 29 | AOFS7 | AOFS6 | AOFS5 | AOFS4 | AOFS3 | AOFS2 | AOFS1 | AOFS0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| AOFS[7:0] | I2S Shift | ||||||||
| These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio sample. | |||||||||
| Default value: 00000000 | |||||||||
| 00000000: offset = 0 BCK (no offset) | |||||||||
| 00000001: ofsset = 1 BCK | |||||||||
| 00000010: offset = 2 BCKs | |||||||||
| . . . | |||||||||
| 11111111: offset = 256 BCKs | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 42 | 2A | RSV | RSV | AUPL1 | AUPL0 | RSV | RSV | AUPR1 | AUPR0 |
| Reset Value | 0 | 1 | 0 | 1 | |||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| AUPL[1:0] | Left DAC Data Path | ||||||||
| These bits control the left channel audio data path connection. | |||||||||
| Default value: 01 | |||||||||
| 00: Zero data (mute) | |||||||||
| 01: Left channel data | |||||||||
| 10: Right channel data | |||||||||
| 11: Reserved (do not set) | |||||||||
| AUPR[1:0] | Right DAC Data Path | ||||||||
| These bits control the right channel audio data path connection. | |||||||||
| Default value: 01 | |||||||||
| 00: Zero data (mute) | |||||||||
| 01: Right channel data | |||||||||
| 10: Left channel data | |||||||||
| 11: Reserved (do not set) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 43 | 2B | RSV | RSV | RSV | PSEL4 | PSEL3 | PSEL2 | PSEL1 | PSEL0 |
| Reset Value | 0 | 0 | 0 | 0 | 1 | ||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| PSEL[4:0] | DSP Program Selection | ||||||||
| These bits select the DSP program to use for audio processing. | |||||||||
| Default value: 00001 | |||||||||
| 00000: Reserved (do not set) | |||||||||
| 00001: 8x/4x/2x FIR interpolation filter with de-emphasis | |||||||||
| 00010: 8x/4x/2x Low latency IIR interpolation filter with de-emphasis | |||||||||
| 00011: High attenuation x8/x4/x2 interpolation filter with de-emphasis | |||||||||
| 00100: Reserved | |||||||||
| 00101: Fixed process flow with configurable parameters | |||||||||
| 00110: Reserved (do not set) | |||||||||
| 00111: 8x Ringing-less low latency FIR interpolation filter without de-emphasis | |||||||||
| 11111: Reserved (do not set) | |||||||||
| others: Reserved (do not set) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 44 | 2C | RSV | RSV | RSV | RSV | RSV | CMDP2 | CMDP1 | CMDP0 |
| Reset Value | 0 | 0 | 0 | ||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| CMDP[2:0] | Clock Missing Detection Period | ||||||||
| These bits set how long both BCK and LRCK keep low before the audio clocks deemed missing and the DAC transitions to powerdown mode. | |||||||||
| Default value: 000 | |||||||||
| 000: about 1 second | |||||||||
| 001: about 2 seconds | |||||||||
| 010: about 3 seconds | |||||||||
| ... | |||||||||
| 111: about 8 seconds | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 59 | 3B | RSV | AMTL2 | AMTL1 | AMTL0 | RSV | AMTR2 | AMTR1 | AMTR0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | |||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| AMTL[2:0] | Auto Mute Time for Left Channel | ||||||||
| These bits specify the length of consecutive zero samples at left channel before the channel can be auto muted. The times shown are for 48 kHz sampling rate and will scale with other rates. | |||||||||
| Default value: 000 | |||||||||
| 000: 21 ms | |||||||||
| 001: 106 ms | |||||||||
| 010: 213 ms | |||||||||
| 011: 533 ms | |||||||||
| 100: 1.07 sec | |||||||||
| 101: 2.13 sec | |||||||||
| 110: 5.33 sec | |||||||||
| 111: 10.66 sec | |||||||||
| AMTR[2:0] | Auto Mute Time for Right Channel | ||||||||
| These bits specify the length of consecutive zero samples at right channel before the channel can be auto muted. The times shown are for 48 kHz sampling rate and will scale with other rates. | |||||||||
| Default value: 000 | |||||||||
| 000: 21 ms | |||||||||
| 001: 106 ms | |||||||||
| 010: 213 ms | |||||||||
| 011: 533 ms | |||||||||
| 100: 1.07 sec | |||||||||
| 101: 2.13 sec | |||||||||
| 110: 5.33 sec | |||||||||
| 111: 10.66 sec | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 60 | 3C | RSV | RSV | RSV | RSV | RSV | RSV | PCTL1 | PCTL0 |
| Reset Value | 0 | 0 | |||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| PCTL[1:0] | Digital Volume Control | ||||||||
| These bits control the behavior of the digital volume. | |||||||||
| Default value: 00 | |||||||||
| 00: The volume for Left and right channels are independent | |||||||||
| 01: Right channel volume follows left channel setting | |||||||||
| 10: Left channel volume follows right channel setting | |||||||||
| 11: Reserved (The volume for Left and right channels are independent) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 61 | 3D | VOLL7 | VOLL6 | VOLL5 | VOLL4 | VOLL3 | VOLL2 | VOLL1 | VOLL0 |
| Reset Value | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | |
| VOLL[7:0] | Left Digital Volume | ||||||||
| These bits control the left channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step. | |||||||||
| Default value: 00110000 | |||||||||
| 00000000: +24.0 dB | |||||||||
| 00000001: +23.5 dB | |||||||||
| . . . | |||||||||
| 00101111: +0.5 dB | |||||||||
| 00110000: 0.0 dB | |||||||||
| 00110001: -0.5 dB | |||||||||
| ... | |||||||||
| 11111110: -103 dB | |||||||||
| 11111111: Mute | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 62 | 3E | VOLR7 | VOLR6 | VOLR5 | VOLR4 | VOLR3 | VOLR2 | VOLR1 | VOLR0 |
| Reset Value | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | |
| VOLR[7:0] | Right Digital Volume | ||||||||
| These bits control the right channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step. | |||||||||
| Default value: 00110000 | |||||||||
| 00000000: +24.0 dB | |||||||||
| 00000001: +23.5 dB | |||||||||
| . . . | |||||||||
| 00101111: +0.5 dB | |||||||||
| 00110000: 0.0 dB | |||||||||
| 00110001: -0.5 dB | |||||||||
| ... | |||||||||
| 11111110: -103 dB | |||||||||
| 11111111: Mute | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 63 | 3F | VNDF1 | VNDF0 | VNDS1 | VNDS0 | VNUF1 | VNUF0 | VNUS1 | VNUS0 |
| Reset Value | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | |
| VNDF[1:0] | Digital Volume Normal Ramp Down Frequency | ||||||||
| These bits control the frequency of the digital volume updates when the volume is ramping down. The setting here is applied to soft mute request, asserted by XSMUTE pin or Page 0 / Register 3. | |||||||||
| Default value: 00 | |||||||||
| 00: Update every 1 FS period | |||||||||
| 01: Update every 2 FS periods | |||||||||
| 10: Update every 4 FS periods | |||||||||
| 11: Directly set the volume to zero (Instant mute) | |||||||||
| VNDS[1:0] | Digital Volume Normal Ramp Down Step | ||||||||
| These bits control the step of the digital volume updates when the volume is ramping down. The setting here is applied to soft mute request, asserted by XSMUTE pin or Page 0 / Register 3. | |||||||||
| Default value: 10 | |||||||||
| 00: Decrement by 4 dB for each update | |||||||||
| 01: Decrement by 2 dB for each update | |||||||||
| 10: Decrement by 1 dB for each update | |||||||||
| 11: Decrement by 0.5 dB for each update | |||||||||
| VNUF[1:0] | Digital Volume Normal Ramp Up Frequency | ||||||||
| These bits control the frequency of the digital volume updates when the volume is ramping up. The setting here is applied to soft unmute request, asserted by XSMUTE pin or Page 0 / Register 3. | |||||||||
| Default value: 00 | |||||||||
| 00: Update every 1 FS period | |||||||||
| 01: Update every 2 FS periods | |||||||||
| 10: Update every 4 FS periods | |||||||||
| 11: Directly restore the volume (Instant unmute) | |||||||||
| VNUS[1:0] | Digital Volume Normal Ramp Up Step | ||||||||
| These bits control the step of the digital volume updates when the volume is ramping up. The setting here is applied to soft unmute request, asserted by XSMUTE pin or Page 0 / Register 3. | |||||||||
| Default value: 10 | |||||||||
| 00: Increment by 4 dB for each update | |||||||||
| 01: Increment by 2 dB for each update | |||||||||
| 10: Increment by 1 dB for each update | |||||||||
| 11: Increment by 0.5 dB for each update | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 64 | 40 | VEDF1 | VEDF0 | VEDS1 | VEDS0 | RSV | RSV | RSV | RSV |
| Reset Value | 0 | 0 | 0 | 0 | |||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| VEDF[1:0] | Digital Volume Emergency Ramp Down Frequency | ||||||||
| These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute. | |||||||||
| Default value: 00 | |||||||||
| 00: Update every 1 FS period | |||||||||
| 01: Update every 2 FS periods | |||||||||
| 10: Update every 4 FS periods | |||||||||
| 11: Directly set the volume to zero (Instant mute) | |||||||||
| VEDS[1:0] | Digital Volume Emergency Ramp Down Step | ||||||||
| These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute. | |||||||||
| Default value: 00 | |||||||||
| 00: Decrement by 4 dB for each update | |||||||||
| 01: Decrement by 2 dB for each update | |||||||||
| 10: Decrement by 1 dB for each update | |||||||||
| 11: Decrement by 0.5 dB for each update | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 65 | 41 | RSV | RSV | RSV | RSV | RSV | ACTL2 | AMLE1 | AMRE0 |
| Reset Value | 1 | 1 | 1 | ||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| ACTL[2:0] | Auto Mute Control | ||||||||
| This bit controls the behavior of the auto mute upon zero sample detection. The time length for zero detection is set with Page 0 / Register 59. | |||||||||
| Default value: 111 | |||||||||
| 0: Auto mute left channel and right channel independently. | |||||||||
| 1: Auto mute left and right channels only when both channels are about to be auto muted. | |||||||||
| AMLE[1:0] | Auto Mute Left Channel | ||||||||
| This bit enables or disables auto mute on right channel. Note that when right channel auto mute is disabled and the Page 0 / Register 65, bit 2 is set to 1, the left channel will also never be auto muted. | |||||||||
| Default value: 11 | |||||||||
| 0: Disable right channel auto mute | |||||||||
| 1: Enable right channel auto mute | |||||||||
| AMRE | Auto Mute Right Channel | ||||||||
| This bit enables or disables auto mute on left channel. Note that when left channel auto mute is disabled and the Page 0 / Register 65, bit 2 is set to 1, the right channel will also never be auto muted. | |||||||||
| Default value: 1 | |||||||||
| 0: Disable left channel auto mute | |||||||||
| 1: Enable left channel auto mute | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 80 | 50 | RSV | RSV | RSV | G1SL4 | G1SL3 | G1SL2 | G1SL1 | G1SL0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | ||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| G1SL[4:0] | GPIO1 Output Selection | ||||||||
| These bits select the signal to output to GPIO1. To actually output the selected signal, the GPIO1 must be set to output mode at Page 0 / Register 8. | |||||||||
| Default value: 00000 | |||||||||
| 00000: off (low) | |||||||||
| 00001: DSP GPIO1 output | |||||||||
| 00010: Register GPIO1 output (Page 0 / Register 86, bit 0) | |||||||||
| 00011: Auto mute flag (asserted when both L and R channels are auto muted) | |||||||||
| 00100: Auto mute flag for left channel | |||||||||
| 00101: Auto mute flag for right channel | |||||||||
| 00110: Clock invalid flag (clock error or clock changing or clock missing) | |||||||||
| 00111: Serial audio interface data output (SDOUT) | |||||||||
| 01000: Analog mute flag for left channel (low active) | |||||||||
| 01001: Analog mute flag for right channel (low active) | |||||||||
| 01010: PLL lock flag | |||||||||
| 01011: Charge pump clock | |||||||||
| 01100: Reserved | |||||||||
| 01101: Reserved | |||||||||
| 01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD | |||||||||
| 01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD | |||||||||
| 010000: PLL Output/4 (Requires Clock Flex Register) | |||||||||
| OTHERS: RESERVED | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 81 | 51 | RSV | RSV | RSV | G2SL4 | G2SL3 | G2SL2 | G2SL1 | G2SL0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | ||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| G2SL[4:0] | GPIO2 Output Selection | ||||||||
| These bits select the signal to output to GPIO2. To actually output the selected signal, the GPIO2 must be set to output mode at Page 0 / Register 8. | |||||||||
| Default value: 00000 | |||||||||
| 00000: off (low) | |||||||||
| 00001: DSP GPIO2 output | |||||||||
| 00010: Register GPIO2 output (Page 0 / Register 86, bit 1) | |||||||||
| 00011: Auto mute flag (asserted when both L and R channels are auto muted) | |||||||||
| 00100: Auto mute flag for left channel | |||||||||
| 00101: Auto mute flag for right channel | |||||||||
| 00110: Clock invalid flag (clock error or clock changing or clock missing) | |||||||||
| 00111: Serial audio interface data output (SDOUT) | |||||||||
| 01000: Analog mute flag for left channel (low active) | |||||||||
| 01001: Analog mute flag for right channel (low active) | |||||||||
| 01010: PLL lock flag | |||||||||
| 01011: Charge pump clock | |||||||||
| 01100: Reserved | |||||||||
| 01101: Reserved | |||||||||
| 01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD | |||||||||
| 01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD | |||||||||
| 010000: PLL Output/4 (Requires Clock Flex Register) | |||||||||
| OTHERS: RESERVED | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 82 | 52 | RSV | RSV | RSV | G3SL4 | G3SL3 | G3SL2 | G3SL1 | G3SL0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | ||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| G3SL[4:0] | GPIO3 Output Selection | ||||||||
| These bits select the signal to output to GPIO3. To actually output the selected signal, the GPIO3 must be set to output mode at Page 0 / Register 8. | |||||||||
| Default value: 00000 | |||||||||
| 0000: off (low) | |||||||||
| 0001: DSP GPIO3 output | |||||||||
| 0010: Register GPIO3 output (Page 0 / Register 86, bit 2) | |||||||||
| 00011: Auto mute flag (asserted when both L and R channels are auto muted) | |||||||||
| 00100: Auto mute flag for left channel | |||||||||
| 00101: Auto mute flag for right channel | |||||||||
| 00110: Clock invalid flag (clock error or clock changing or clock missing) | |||||||||
| 00111: Serial audio interface data output (SDOUT) | |||||||||
| 01000: Analog mute flag for left channel (low active) | |||||||||
| 01001: Analog mute flag for right channel (low active) | |||||||||
| 01010: PLL lock flag | |||||||||
| 01011: Charge pump clock | |||||||||
| 01100: Reserved | |||||||||
| 01101: Reserved | |||||||||
| 01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD | |||||||||
| 01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD | |||||||||
| 010000: PLL Output/4 (Requires Clock Flex Register) | |||||||||
| OTHERS: RESERVED | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 83 | 53 | RSV | RSV | RSV | G4SL4 | G4SL3 | G4SL2 | G4SL1 | G4SL0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | ||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| G4SL[4:0] | GPIO4 Output Selection | ||||||||
| These bits select the signal to output to GPIO4. To actually output the selected signal, the GPIO4 must be set to output mode at Page 0 / Register 8. | |||||||||
| Default value: 00000 | |||||||||
| 00000: off (low) | |||||||||
| 00001: DSP GPIO4 output | |||||||||
| 00010: Register GPIO4 output (Page 0 / Register 86, bit 3) | |||||||||
| 00011: Auto mute flag (asserted when both L and R channels are auto muted) | |||||||||
| 00100: Auto mute flag for left channel | |||||||||
| 00101: Auto mute flag for right channel | |||||||||
| 00110: Clock invalid flag (clock error or clock changing or clock missing) | |||||||||
| 00111: Serial audio interface data output (SDOUT) | |||||||||
| 01000: Analog mute flag for left channel (low active) | |||||||||
| 01001: Analog mute flag for right channel (low active) | |||||||||
| 01010: PLL lock flag | |||||||||
| 01011: Charge pump clock | |||||||||
| 01100: Reserved | |||||||||
| 01101: Reserved | |||||||||
| 01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD | |||||||||
| 01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD | |||||||||
| 010000: PLL Output/4 (Requires Clock Flex Register) | |||||||||
| OTHERS: RESERVED | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 84 | 54 | RSV | RSV | RSV | G5SL4 | G5SL3 | G5SL2 | G5SL1 | G5SL0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | ||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| G5SL[4:0] | GPIO5 Output Selection | ||||||||
| These bits select the signal to output to GPIO5. To actually output the selected signal, the GPIO5 must be set to output mode at Page 0 / Register 8. | |||||||||
| Default value: 00000 | |||||||||
| 00000: off (low) | |||||||||
| 00001: DSP GPIO5 output | |||||||||
| 00010: Register GPIO5 output (Page 0 / Register 86, bit 4 | |||||||||
| 00011: Auto mute flag (asserted when both L and R channels are auto muted) | |||||||||
| 00100: Auto mute flag for left channel | |||||||||
| 00101: Auto mute flag for right channel | |||||||||
| 00110: Clock invalid flag (clock error or clock changing or clock missing) | |||||||||
| 00111: Serial audio interface data output (SDOUT) | |||||||||
| 01000: Analog mute flag for left channel (low active) | |||||||||
| 01001: Analog mute flag for right channel (low active) | |||||||||
| 01010: PLL lock flag | |||||||||
| 01011: Charge pump clock | |||||||||
| 01100: Reserved | |||||||||
| 01101: Reserved | |||||||||
| 01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD | |||||||||
| 01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD | |||||||||
| 010000: PLL Output/4 (Requires Clock Flex Register) | |||||||||
| OTHERS: RESERVED | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 85 | 55 | RSV | RSV | RSV | G6SL4 | G6SL3 | G6SL2 | G6SL1 | G6SL0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | ||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| G6SL[4:0] | GPIO6 Output Selection | ||||||||
| These bits select the signal to output to GPIO6. To actually output the selected signal, the GPIO6 must be set to output mode at Page 0 / Register 8. | |||||||||
| Default value: 00000 | |||||||||
| 00000: off (low) | |||||||||
| 00001: DSP GPIO6 output | |||||||||
| 00010: Register GPIO6 output (Page 0 / Register 86, bit 5) | |||||||||
| 00011: Auto mute flag (asserted when both L and R channels are auto muted) | |||||||||
| 00100: Auto mute flag for left channel | |||||||||
| 00101: Auto mute flag for right channel | |||||||||
| 00110: Clock invalid flag (clock error or clock changing or clock missing) | |||||||||
| 00111: Serial audio interface data output (SDOUT) | |||||||||
| 01000: Analog mute flag for left channel (low active) | |||||||||
| 01001: Analog mute flag for right channel (low active) | |||||||||
| 01010: PLL lock flag | |||||||||
| 01011: Charge pump clock | |||||||||
| 01100: Reserved | |||||||||
| 01101: Reserved | |||||||||
| 01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD | |||||||||
| 01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD | |||||||||
| 010000: PLL Output/4 (Requires Clock Flex Register) | |||||||||
| OTHERS: RESERVED | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 86 | 56 | RSV | RSV | GOUT5 | GOUT4 | GOUT3 | GOUT2 | GOUT1 | GOUT0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | |||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| GOUT5 | GPIO6 Output Control | ||||||||
| This bit controls the GPIO6 output when the selection at Page 0 / Register 85 is set to 0010 (register output) | |||||||||
| Default value: 0 | |||||||||
| 0: Output low | |||||||||
| 1: Output high | |||||||||
| GOUT4 | GPIO5 Output Control | ||||||||
| This bit controls the GPIO5 output when the selection at Page 0 / Register 84 is set to 0010 (register output) | |||||||||
| Default value: 0 | |||||||||
| 0: Output low | |||||||||
| 1: Output high | |||||||||
| GOUT3 | GPIO4 Output Control | ||||||||
| This bit controls the GPIO4 output when the selection at Page 0 / Register 83 is set to 0010 (register output) | |||||||||
| Default value: 0 | |||||||||
| 0: Output low | |||||||||
| 1: Output high | |||||||||
| GOUT2 | GPIO3 Output Control | ||||||||
| This bit controls the GPIO3 output when the selection at Page 0 / Register 82 is set to 0010 (register output) | |||||||||
| Default value: 0 | |||||||||
| 0: Output low | |||||||||
| 1: Output high | |||||||||
| GOUT1 | GPIO2 Output Control | ||||||||
| This bit controls the GPIO2 output when the selection at Page 0 / Register 81 is set to 0010 (register output) | |||||||||
| Default value: 0 | |||||||||
| 0: Output low | |||||||||
| 1: Output high | |||||||||
| GOUT0 | GPIO1 Output Control | ||||||||
| This bit controls the GPIO1 output when the selection at Page 0 / Register 80 is set to 0010 (register output) | |||||||||
| Default value: 0 | |||||||||
| 0: Output low | |||||||||
| 1: Output high | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 87 | 57 | RSV | RSV | GINV5 | GINV4 | GINV3 | GINV2 | GINV1 | GINV0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | |||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| GINV5 | GPIO6 Output Inversion | ||||||||
| This bit controls the polarity of GPIO6 output. When set to 1, the output will be inverted for any signal being selected. | |||||||||
| Default value: 0 | |||||||||
| 0: Non-inverted | |||||||||
| 1: Inverted | |||||||||
| GINV4 | GPIO5 Output Inversion | ||||||||
| This bit controls the polarity of GPIO5 output. When set to 1, the output will be inverted for any signal being selected. | |||||||||
| Default value: 0 | |||||||||
| 0: Non-inverted | |||||||||
| 1: Inverted | |||||||||
| GINV3 | GPIO4 Output Inversion | ||||||||
| This bit controls the polarity of GPIO4 output. When set to 1, the output will be inverted for any signal being selected. | |||||||||
| Default value: 0 | |||||||||
| 0: Non-inverted | |||||||||
| 1: Inverted | |||||||||
| GINV2 | GPIO3 Output Inversion | ||||||||
| This bit controls the polarity of GPIO3 output. When set to 1, the output will be inverted for any signal being selected. | |||||||||
| Default value: 0 | |||||||||
| 0: Non-inverted | |||||||||
| 1: Inverted | |||||||||
| GINV1 | GPIO2 Output Inversion | ||||||||
| This bit controls the polarity of GPIO2 output. When set to 1, the output will be inverted for any signal being selected. | |||||||||
| Default value: 0 | |||||||||
| 0: Non-inverted | |||||||||
| 1: Inverted | |||||||||
| GINV0 | GPIO1 Output Inversion | ||||||||
| This bit controls the polarity of GPIO1 output. When set to 1, the output will be inverted for any signal being selected. | |||||||||
| Default value: 0 | |||||||||
| 0: Non-inverted | |||||||||
| 1: Inverted | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 90 | 5A | RSV | RSV | RSV | L1OV | R1OV | L2OV | R2OV | SFOV |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| L1OV | Left1 Overflow (Read Only) | ||||||||
| This bit indicates whether the left channel of DSP first output port has overflow. This bit is sticky and is cleared when read. | |||||||||
| 0: No overflow | |||||||||
| 1: Overflow occurred | |||||||||
| R1OV | Right1 Overflow (Read Only) | ||||||||
| The bit indicates whether the right channel of DSP first output port has overflow. This bit is sticky and is cleared when read. | |||||||||
| 0: No overflow | |||||||||
| 1: Overflow occurred | |||||||||
| L2OV | Left2 Overflow (Read Only) | ||||||||
| This bit indicates whether the left channel of DSP second output port has overflow. This bit is sticky and is cleared when read. | |||||||||
| 0: No overflow | |||||||||
| 1: Overflow occurred | |||||||||
| R2OV | Right2 Overflow (Read Only) | ||||||||
| The bit indicates whether the right channel of DSP second output port has overflow. This bit is sticky and is cleared when read. | |||||||||
| 0: No overflow | |||||||||
| 1: Overflow occurred | |||||||||
| SFOV | Shifter Overflow (Read Only) | ||||||||
| This bit indicates whether overflow occurred in the DSP shifter (possible sample corruption). This bit is sticky and is cleared when read. | |||||||||
| 0: No overflow | |||||||||
| 1: Overflow occurred | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 91 | 5B | RSV | DTFS2 | DTFS1 | DTFS0 | DTSR3 | DTSR2 | DTSR1 | DTSR0 |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| DTFS[2:0] | Detected FS (Read Only) | ||||||||
| These bits indicate the currently detected audio sampling rate. | |||||||||
| 000: Error (Out of valid range) | |||||||||
| 001: 8 kHz | |||||||||
| 010: 16 kHz | |||||||||
| 011: 32-48 kHz | |||||||||
| 100: 88.2-96 kHz | |||||||||
| 101: 176.4-192 kHz | |||||||||
| 110: 384 kHz | |||||||||
| DTSR[3:0] | Detected SCK Ratio (Read Only) | ||||||||
| These bits indicate the currently detected SCK ratio. Note that even if the SCK ratio is not indicated as error, clock error might still be flagged due to incompatible combination with the sampling rate. Specifically the SCK ratio must be high enough to allow enough DSP cycles for minimal audio processing when PLL is disabled. The absolute SCK frequency must also be lower than 50 MHz. | |||||||||
| 0000: Ratio error (The SCK ratio is not allowed) | |||||||||
| 0001: SCK = 32 FS | |||||||||
| 0010: SCK = 48 FS | |||||||||
| 0011: SCK = 64 FS | |||||||||
| 0100: SCK = 128 FS | |||||||||
| 0101: SCK = 192 FS | |||||||||
| 0110: SCK = 256 FS | |||||||||
| 0111: SCK = 384 FS | |||||||||
| 1000: SCK = 512 FS | |||||||||
| 1001: SCK = 768 FS | |||||||||
| 1010: SCK = 1024 FS | |||||||||
| 1011: SCK = 1152 FS | |||||||||
| 1100: SCK = 1536 FS | |||||||||
| 1101: SCK = 2048 FS | |||||||||
| 1110: SCK = 3072 FS | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 92 | 5C | RSV | RSV | RSV | RSV | RSV | RSV | RSV | DTBR8 |
| Reset Value | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 93 | 5D | DTBR7 | DTBR6 | DTBR5 | DTBR4 | DTBR3 | DTBR2 | DTBR1 | DTBR0 |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| DTBR[8:0] | Detected BCK Ratio (MSB) (Read Only) | ||||||||
| These bits indicate the currently detected BCK ratio, that is, the number of BCK clocks in one audio frame. Note that for extreme case of BCK = 1 FS (which is not usable anyway), the detected ratio will be unreliable. | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 94 | 5E | RSV | CDST | PLL-L | LrckBck | fS-SCKr | SCKval | BCKval | fSval |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| CDST | Clock Detector Status (Read Only) | ||||||||
| This bit indicates whether the SCK clock is present or not. | |||||||||
| 0: SCK is present | |||||||||
| 1: SCK is missing (halted) | |||||||||
| PLL-L | PLL locked (Read Only) | ||||||||
| This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled. | |||||||||
| 0: PLL is locked | |||||||||
| 1: PLL is unlocked | |||||||||
| LrckBck | LRCK-BCK present (Read Only) | ||||||||
| This bit indicates whether the both LRCK and BCK are missing (tied low) or not. | |||||||||
| 0: LRCK and/or BCK is present | |||||||||
| 1: LRCK and BCK are missing | |||||||||
| fS-SCKr | Sample rate SCK ratio valid (Read Only) | ||||||||
| This bit indicates whether the combination of current sampling rate and SCK ratio is valid for clock auto set. | |||||||||
| 0: The combination of FS/SCK ratio is valid | |||||||||
| 1: Error (clock auto set is not possible) | |||||||||
| SCKval | SCK valid (Read Only) | ||||||||
| This bit indicates whether the SCK is valid or not. The SCK ratio must be detectable to be valid. There is a limitation with this flag, that is, when the low period of LRCK is less than or equal to 5 BCKs, this flag will be asserted (SCK invalid reported). | |||||||||
| 0: SCK is valid | |||||||||
| 1: SCK is invalid | |||||||||
| BCKval | BCK valid (Read Only) | ||||||||
| This bit indicates whether the BCK is valid or not. The BCK ratio must be stable and in the range of 32-256FS to be valid. | |||||||||
| 0: BCK is valid | |||||||||
| 1: BCK is invalid | |||||||||
| fSval | fS valid (Read Only) | ||||||||
| This bit indicated whether the audio sampling rate is valid or not. The sampling rate must be detectable to be valid. There is a limitation with this flag, that is when this flag is asserted and Page 0 / Register 37 is set to ignore all asserted error flags such that the DAC recovers, this flag will be de-asserted (sampling rate invalid not reported anymore). | |||||||||
| 0: Sampling rate is valid | |||||||||
| 1: Sampling rate is invalid | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 95 | 5F | RSV | RSV | RSV | LTSH | RSV | CKMF | CSRF | CERF |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| LTSH | Latched Clock Halt (Read Only) | ||||||||
| This bit indicates whether SCK halt has occurred. The bit is cleared when read. | |||||||||
| 0: SCK halt has not occurred | |||||||||
| 1: SCK halt has occurred since last read | |||||||||
| CKMF | Clock Missing (Read Only) | ||||||||
| This bit indicates whether the LRCK and BCK are missing (tied low). | |||||||||
| 0: LRCK and/or BCK is present | |||||||||
| 1: LRCK and BCK are missing | |||||||||
| CSRF | Clock Resync Request (Read Only) | ||||||||
| This bit indicates whether the clock resynchronization is in progress. | |||||||||
| 0: Not resynchronizing | |||||||||
| 1: Clock resynchronization is in progress | |||||||||
| CERF | Clock Error (Read Only) | ||||||||
| This bit indicates whether a clock error is being reported. | |||||||||
| 0: Clock is valid | |||||||||
| 1: Clock is invalid (Error) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 108 | 6C | RSV | RSV | RSV | RSV | RSV | RSV | AMLM | AMRM |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| AMLM | Left Analog Mute Monitor (Read Only) | ||||||||
| This bit is a monitor for left channel analog mute status. | |||||||||
| 0: Mute | |||||||||
| 1: Unmute | |||||||||
| AMRM | Right Analog Mute Monitor (Read Only) | ||||||||
| This bit is a monitor for right channel analog mute status. | |||||||||
| 0: Mute | |||||||||
| 1: Unmute | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 109 | 6D | RSV | RSV | RSV | SDTM | RSV | RSV | RSV | SHTM |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| SDTM | Short detect monitor (Read Only) | ||||||||
| This bit indicates whether line output short is occuring. | |||||||||
| 0: Normal (No short) | |||||||||
| 1: Line output is being shorted | |||||||||
| SHTM | Short detected monitor (Read Only) | ||||||||
| This bit indicates whether line output short has occurred since last read. This bit is sticky and is cleared when read. | |||||||||
| 0: No short | |||||||||
| 1: Line output short occurred | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 114 | 72 | RSV | RSV | RSV | RSV | RSV | RSV | MTST1 | MTST0 |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| MTST[1:0] | MUTEZ status (Read Only) | ||||||||
| These bits indicate the output of the XSMUTE level decoder for monitoring purpose. | |||||||||
| 11: 0.7 VDD ≤ XSMUTE | |||||||||
| 01: 0.3 VDD ≤ XSMUTE < 0.7 VDD | |||||||||
| 00: 0.3 VDD > XSMUTE | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 115 | 73 | RSV | RSV | RSV | RSV | RSV | RSV | FSMM1 | FSMM0 |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| FSMM[1:0] | FS Speed Mode Monitor (Read Only) | ||||||||
| These bits indicate the actual FS operation mode being used. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled. | |||||||||
| 00: Single speed (FS ≤ 48 kHz) | |||||||||
| 01: Double speed (48 kHz < FS ≤ 96 kHz) | |||||||||
| 10: Quad speed (96 kHz < FS ≤ 192 kHz) | |||||||||
| 11: Octal speed (192 kHz < FS ≤ 384 kHz) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 118 | 76 | BOTM | RSV | RSV | RSV | PSTM3 | PSTM2 | PSTM1 | PSTM0 |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| BOTM | DSP Boot Done Flag (Read Only) | ||||||||
| This bit indicates whether the DSP boot is completed. | |||||||||
| 0: DSP is booting | |||||||||
| 1: DSP boot completed | |||||||||
| PSTM[3:0] | Power State (Read Only) | ||||||||
| These bits indicate the current power state of the DAC. | |||||||||
| 0000: Powerdown | |||||||||
| 0001: Wait for CP voltage valid | |||||||||
| 0010: Calibration | |||||||||
| 0011: Calibration | |||||||||
| 0100: Volume ramp up | |||||||||
| 0101: Run (Playing) | |||||||||
| 0110: Line output short / Low impedance | |||||||||
| 0111: Volume ramp down | |||||||||
| 1000: Standby | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 119 | 77 | RSV | RSV | GPIN5 | GPIN4 | GPIN3 | GPIN2 | GPIN1 | RSV |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| GPIN[5:0] | GPIO Input States (Read Only) | ||||||||
| This bit indicates the logic level at GPIO6 pin. | |||||||||
| 0: Low | |||||||||
| 1: High | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 120 | 78 | RSV | RSV | RSV | AMFL | RSV | RSV | RSV | AMFR |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| AMFL | Auto Mute Flag for Left Channel (Read Only) | ||||||||
| This bit indicates the auto mute status for left channel. | |||||||||
| 0: Not auto muted | |||||||||
| 1: Auto muted | |||||||||
| AMFR | Auto Mute Flag for Right Channel (Read Only) | ||||||||
| This bit indicates the auto mute status for right channel. | |||||||||
| 0: Not auto muted | |||||||||
| 1: Auto muted | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 121 | 79 | RSV | RSV | RSV | RSV | RSV | RSV | RSV | DAMD |
| Reset Value | 0 | ||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| DAMD | DAC Mode | ||||||||
| This bit controls the DAC architecture to vary the DAC auditory signature. | |||||||||
| Default value: 0 | |||||||||
| 0: Mode1 - New hyper-advanced current-segment architecture | |||||||||
| 1: Mode2 - Classic PCM1792 advanced current-segment architecture | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 122 | 7A | RSV | RSV | RSV | RSV | RSV | RSV | RSV | EIFM |
| Reset Value | 0 | ||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| EIFM | External Interpolation Filter Mode | ||||||||
| This bit enables or disables the PCM1792 External Interpolation Filter Mode. This mode is used with a PCM1792 in external digital filter mode. | |||||||||
| Default value: 0 | |||||||||
| 0: Normal mode | |||||||||
| 1: External Interpolation Filter Mode | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 123 | 7B | RSV | G1MC2 | G1MC1 | G1MC0 | RSV | G2MC2 | G2MC1 | G2MC0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | |||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| G1MC[2:0] | GPIO1 output for External Interpolation Filter Mode | ||||||||
| These bits select a signal to be output to GPIO1 in External Interpolation Filter mode. | |||||||||
| Default value: 000 | |||||||||
| 000: Logic low | |||||||||
| 001: MS | |||||||||
| 010: BCK (256FS) | |||||||||
| 011: WDCK (8FS) | |||||||||
| 100: DATAL | |||||||||
| 101: DATAR | |||||||||
| 110: Raw DIN (from DIN pin) | |||||||||
| 111: Raw LRCK (from LRCK pin) | |||||||||
| G2MC[2:0] | GPIO2 output for External Interpolation Filter Mode | ||||||||
| These bits select a signal to be output to GPIO2 in External Interpolation Filter mode. | |||||||||
| Default value: 000 | |||||||||
| 000: Logic low | |||||||||
| 001: MS | |||||||||
| 010: BCK (256FS) | |||||||||
| 011: WDCK (8FS) | |||||||||
| 100: DATAL | |||||||||
| 101: DATAR | |||||||||
| 110: Raw DIN (from DIN pin) | |||||||||
| 111: Raw LRCK (from LRCK pin) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 124 | 7C | RSV | G3MC2 | G3MC1 | G3MC0 | RSV | G4MC2 | G4MC1 | G4MC0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | |||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| G3MC[2:0] | GPIO3 output for External Interpolation Filter Mode | ||||||||
| These bits select a signal to be output to GPIO3 in External Interpolation Filter Mode. | |||||||||
| Default value: 000 | |||||||||
| 000: Logic low | |||||||||
| 001: MS | |||||||||
| 010: BCK (256FS) | |||||||||
| 011: WDCK (8FS) | |||||||||
| 100: DATAL | |||||||||
| 101: DATAR | |||||||||
| 110: Raw DIN (from DIN pin) | |||||||||
| 111: Raw LRCK (from LRCK pin) | |||||||||
| G4MC[2:0] | GPIO4 output for External Interpolation Filter Mode | ||||||||
| These bits select a signal to be output to GPIO4 in External Interpolation Filter Mode. | |||||||||
| Default value: 000 | |||||||||
| 000: Logic low | |||||||||
| 001: MS | |||||||||
| 010: BCK (256FS) | |||||||||
| 011: WDCK (8FS) | |||||||||
| 100: DATAL | |||||||||
| 101: DATAR | |||||||||
| 110: Raw DIN (from DIN pin) | |||||||||
| 111: Raw LRCK (from LRCK pin) | |||||||||
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 125 | 7D | RSV | G5MC2 | G5MC1 | G5MC0 | RSV | G6MC2 | G6MC1 | G6MC0 |
| Reset Value | 0 | 0 | 0 | 0 | 0 | 0 | |||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| G5MC[2:0] | GPIO5 output for External Interpolation Filter Mode | ||||||||
| These bits select a signal to be output to GPIO5 in External Interpolation Filter mode. | |||||||||
| Default value: 000 | |||||||||
| 000: Logic low | |||||||||
| 001: MS | |||||||||
| 010: BCK (256FS) | |||||||||
| 011: WDCK (8FS) | |||||||||
| 100: DATAL | |||||||||
| 101: DATAR | |||||||||
| 110: Raw DIN (from DIN pin) | |||||||||
| 111: Raw LRCK (from LRCK pin) | |||||||||
| G6MC[2:0] | GPIO6 output for External Interpolation Filter Mode | ||||||||
| These bits select a signal to be output to GPIO6 in External Interpolation Filter mode. | |||||||||
| Default value: 000 | |||||||||
| 000: Logic low | |||||||||
| 001: MS | |||||||||
| 010: BCK (256FS) | |||||||||
| 011: WDCK (8FS) | |||||||||
| 100: DATAL | |||||||||
| 101: DATAR | |||||||||
| 110: Raw DIN (from DIN pin) | |||||||||
| 111: Raw LRCK (from LRCK pin) | |||||||||