SBASA64 December   2020 PCMD3140

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 6.9  Switching Characteristics: TDM, I2S or LJ Interface
    10. 6.10 Timing Requirements: PDM Digital Microphone Interface
    11. 6.11 Switching Characteristics: PDM Digial Microphone Interface
    12. 6.12 Timing Diagrams
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Reference Voltage
      4. 7.3.4 Microphone Bias
      5. 7.3.5 Digital PDM Microphone Record Channel
      6. 7.3.6 Signal-Chain Processing
        1. 7.3.6.1 Programmable Digital Volume Control
        2. 7.3.6.2 Programmable Channel Gain Calibration
        3. 7.3.6.3 Programmable Channel Phase Calibration
        4. 7.3.6.4 Programmable Digital High-Pass Filter
        5. 7.3.6.5 Programmable Digital Biquad Filters
        6. 7.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 7.3.6.7 Configurable Digital Decimation Filters
          1. 7.3.6.7.1 Linear Phase Filters
            1. 7.3.6.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 7.3.6.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 7.3.6.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 7.3.6.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 7.3.6.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 7.3.6.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 7.3.6.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 7.3.6.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 7.3.6.7.1.9 Sampling Rate 768 kHz or 705.6 kHz
          2. 7.3.6.7.2 Low-Latency Filters
            1. 7.3.6.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.6.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.6.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.6.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.6.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 7.3.6.7.2.6 Sampling Rate 192 kHz or 176.4 kHz
          3. 7.3.6.7.3 Ultra-Low-Latency Filters
            1. 7.3.6.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.6.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.6.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.6.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.6.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 7.3.6.7.3.6 Sampling Rate 192 kHz or 176.4 kHz
            7. 7.3.6.7.3.7 Sampling Rate 384 kHz or 352.8 kHz
      7. 7.3.7 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode or Software Shutdown
      2. 7.4.2 Active Mode
      3. 7.4.3 Software Reset
    5. 7.5 Programming
      1. 7.5.1 Control Serial Interfaces
        1. 7.5.1.1 I2C Control Interface
          1. 7.5.1.1.1 General I2C Operation
          2. 7.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 7.5.1.1.2.1 I2C Single-Byte Write
            2. 7.5.1.1.2.2 I2C Multiple-Byte Write
            3. 7.5.1.1.2.3 I2C Single-Byte Read
            4. 7.5.1.1.2.4 I2C Multiple-Byte Read
    6. 7.6 Register Maps
      1. 7.6.1 Page 0 Registers
      2. 7.6.2 Page 1 Registers
      3. 7.6.3 Programmable Coefficient Registers
        1. 7.6.3.1 Programmable Coefficient Registers: Page 2
        2. 7.6.3.2 Programmable Coefficient Registers: Page 3
        3. 7.6.3.3 Programmable Coefficient Registers: Page 4
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Four-Channel Digital PDM Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RTE|20
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • 4-channel PDM microphones simultaneous conversion
  • PDM input to TDM or I2S output converter performance:
    • 127-dB dynamic range (DR) with high-performance, 5th-order PDM input
    • 117-dB dynamic range (DR) with high-performance, 4th-order PDM input
  • Channel summing mode, DR performance with high-performance, 4th-order PDM input:
    • 120-dB, 2-channel summing
  • Programmable PDM clock output :
    • 768 kHz to 6.144 MHz
  • Programmable output sample rate (fS) :
    • 8 kHz to 768 kHz
  • Programmable channel settings:
    • Digital volume control: –100 dB to 27 dB
    • Gain calibration: 0.1-dB resolution
    • Phase calibration: 163-ns resolution
  • Microphone bias or supply voltage generation
  • Low-latency signal processing filter selection
  • Programmable HPF and biquad digital filters
  • I2C control
  • Integrated high-performance audio PLL
  • Automatic clock divider setting configurations
  • Audio serial data interface:
    • Format: TDM, I2S, or left-justified (LJ)
    • Word length: 16 bits, 20 bits, 24 bits, or 32 bits
    • Master or slave interface
  • Single-supply operation: 3.3 V or 1.8 V
  • I/O-supply operation: 3.3 V or 1.8 V
  • Power consumption for 1.8-V supply:
    • TBD/channel at 16-kHz sample rate
    • TBD/channel at 48-kHz sample rate