JAJSGH0C November   2018  – August 2019 SN6505A-Q1 , SN6505B-Q1 , SN6505D-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. Table 1. Absolute Maximum Ratings
    2. Table 2. ESD Ratings
    3. Table 3. Recommended Operating Conditions
    4. Table 4. Thermal Information
    5. Table 5. Electrical Characteristics
    6. Table 6. Timing Requirements
    7. 7.1      Typical Characteristics, SN6505A-Q1
    8. 7.2      Typical Characteristics, SN6505B-Q1 or SN6505D-Q1
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Push-Pull Converter
      2. 9.3.2 Core Magnetization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start-Up Mode
        1. 9.4.1.1 Soft-Start
      2. 9.4.2 Operating Mode
      3. 9.4.3 Shutdown-Mode
      4. 9.4.4 Spread Spectrum Clocking
      5. 9.4.5 External Clock Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Drive Capability
        2. 10.2.2.2 LDO Selection
        3. 10.2.2.3 Diode Selection
        4. 10.2.2.4 Capacitor Selection
        5. 10.2.2.5 Transformer Selection
          1. 10.2.2.5.1 V-t Product Calculation
          2. 10.2.2.5.2 Turns Ratio Estimate
          3. 10.2.2.5.3 Recommended Transformers
      3. 10.2.3 Application Curves
      4. 10.2.4 System Examples
        1. 10.2.4.1 Higher Output Voltage Designs
        2. 10.2.4.2 Application Circuits
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Table 5. Electrical Characteristics

over full-range of recommended operating conditions, unless otherwise noted. All typical values are at TA = 25°C, VCC = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE SUPPLY
I(Vcc) Supply Current (2.8 V ≤ VCC ≤ 5.5 V) (SN6505A-Q1) RL = 50 Ω 1 1.4 mA
Supply Current (2.8 V ≤ VCC ≤ 5.5 V) (SN6505B-Q1 and SN6505D-Q1) RL = 50 Ω 1.56 2.3 mA
IIH Leakage Current on EN and CLK pin EN / CLK = VCC 10 20 µA
IDIS VCC current for EN = 0 0.1 µA
ILKG(D1)
ILKG(D2)
Leakage Current on D1, D2 for EN=0 Voltage of D1, D2 = VCC 0.1 µA
VCC+ (UVLO) Positive-going UVLO threshold 2.25 V
VCC- (UVLO) Negative-going UVLO threshold 1.7 V
VHYS (UVLO1) UVLO threshold hysteresis 0.3 V
VIN(ON) EN, CLK pin logic high threshold 0.7 VCC
VIN(OFF) EN, CLK pin logic low threshold 0.3 VCC
VIN(HYS) EN, CLK pin threshold hysteresis 0.2 VCC
CLK
FSW D1, D2 average switching Frequency (SN6505A-Q1) RL = 50 Ω to VCC; Refer to Figure 36 138 160 203 Khz
D1, D2 average switching Frequency (SN6505B-Q1 and SN6505D-Q1) RL = 50 Ω to VCC; Refer to Figure 36. 363 424 517 kHz
F(EXT) External clock frequency on CLK pin (SN6505A-Q1) 100 600 kHz
External clock frequency on CLK pin (SN6505B-Q1 and SN6505D-Q1) 100 1600 kHz
OUTPUT STAGE
DMM Average ON time mismatch between D1 and D2 RL = 50 Ω 0%
R(ON) Output switch on resistance VCC = 4.5 V, ID1, ID2 = 1 A 0.16 0.25 Ω
VCC = 2.8 V, ID1, ID2 = 1 A 0.19 0.31 Ω
VCC = 2.25 V, ID1, ID2 = 0.5 A 0.21 0.45 Ω
V(SLEW) Voltage slew rates on D1 and D2 for SN6505A-Q1 RL = 50 Ω to VCC; Refer to Figure 36 48 V/µs
I(SLEW) Current slew rates at D1 and D2 for SN6505A-Q1 RL = 5 Ω through transformer;
Refer to Figure 37
11 A/µs
V(SLEWHF) Voltage slew rates on D1 and D2 for SN6505B-Q1 and SN6505D-Q1 RL = 50 Ω to VCC; Refer to Figure 36 152 V/µs
I(SLEWHF) Current slew rates at D1 and D2 for SN6505B-Q1 and SN6505D-Q1 RL = 5 Ω through transformer;
Refer to Figure 37
41 A/µs
ILIM Current clamp limit (2.8 V < VCC ≤ 5.5V ) 1.42 1.75 2.15 A
Current clamp limit (2.25 V ≤ VCC ≤ 2.8 V) 0.65 1.85 A
THERMAL SHUT DOWN
TSD+ TSD turn on temperature 154 168 181 °C
TSD- TSD turn off temperature 135 150 166 °C
TSD- TSD hysteresis 13 17 °C