JAJSGH0C November   2018  – August 2019 SN6505A-Q1 , SN6505B-Q1 , SN6505D-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. Table 1. Absolute Maximum Ratings
    2. Table 2. ESD Ratings
    3. Table 3. Recommended Operating Conditions
    4. Table 4. Thermal Information
    5. Table 5. Electrical Characteristics
    6. Table 6. Timing Requirements
    7. 7.1      Typical Characteristics, SN6505A-Q1
    8. 7.2      Typical Characteristics, SN6505B-Q1 or SN6505D-Q1
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Push-Pull Converter
      2. 9.3.2 Core Magnetization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start-Up Mode
        1. 9.4.1.1 Soft-Start
      2. 9.4.2 Operating Mode
      3. 9.4.3 Shutdown-Mode
      4. 9.4.4 Spread Spectrum Clocking
      5. 9.4.5 External Clock Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Drive Capability
        2. 10.2.2.2 LDO Selection
        3. 10.2.2.3 Diode Selection
        4. 10.2.2.4 Capacitor Selection
        5. 10.2.2.5 Transformer Selection
          1. 10.2.2.5.1 V-t Product Calculation
          2. 10.2.2.5.2 Turns Ratio Estimate
          3. 10.2.2.5.3 Recommended Transformers
      3. 10.2.3 Application Curves
      4. 10.2.4 System Examples
        1. 10.2.4.1 Higher Output Voltage Designs
        2. 10.2.4.2 Application Circuits
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Push-Pull Converter

Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary (see Figure 38).

SN6505A-Q1 SN6505B-Q1 SN6505D-Q1 push_pull_conv_llsea0.gifFigure 38. Switching Cycles of a Push-Pull Converter

When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negative voltage potential at the lower primary end with regards to the VIN potential at the center-tap.

At the same time the voltage across the upper half of the primary is such that the upper primary end is positive with regards to the center-tap in order to maintain the previously established current flow through Q2, which now has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a voltage potential at the open end of the primary of 2×VIN with regards to ground.

Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current starting from the upper secondary end flows through CR1, charges capacitor C, and returns through the load impedance RL back to the center-tap.

When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse. Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2 is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2, charging the capacitor and returning through the load to the center-tap.