JAJSGH0C November   2018  – August 2019 SN6505A-Q1 , SN6505B-Q1 , SN6505D-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. Table 1. Absolute Maximum Ratings
    2. Table 2. ESD Ratings
    3. Table 3. Recommended Operating Conditions
    4. Table 4. Thermal Information
    5. Table 5. Electrical Characteristics
    6. Table 6. Timing Requirements
    7. 7.1      Typical Characteristics, SN6505A-Q1
    8. 7.2      Typical Characteristics, SN6505B-Q1 or SN6505D-Q1
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Push-Pull Converter
      2. 9.3.2 Core Magnetization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start-Up Mode
        1. 9.4.1.1 Soft-Start
      2. 9.4.2 Operating Mode
      3. 9.4.3 Shutdown-Mode
      4. 9.4.4 Spread Spectrum Clocking
      5. 9.4.5 External Clock Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Drive Capability
        2. 10.2.2.2 LDO Selection
        3. 10.2.2.3 Diode Selection
        4. 10.2.2.4 Capacitor Selection
        5. 10.2.2.5 Transformer Selection
          1. 10.2.2.5.1 V-t Product Calculation
          2. 10.2.2.5.2 Turns Ratio Estimate
          3. 10.2.2.5.3 Recommended Transformers
      3. 10.2.3 Application Curves
      4. 10.2.4 System Examples
        1. 10.2.4.1 Higher Output Voltage Designs
        2. 10.2.4.2 Application Circuits
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Application Information

The SN6505x-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC/DC converters using the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive, comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output signals which alternately turn the two output transistors on and off.

SN6505A-Q1 SN6505B-Q1 SN6505D-Q1 op_tim_bd_sllsep9.gifFigure 40. Block Diagram and Output Timing With Break-Before-Make Action

The output frequency of the oscillator is divided down by an asynchronous divider that provides two complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gate-drive signals for the output transistors Q1 and Q2. As shown in Figure 41, before either one of the gates can assume logic high, there must be a short time period during which both signals are low and both transistors are high-impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of the primary.

SN6505A-Q1 SN6505B-Q1 SN6505D-Q1 Figure15_sllsep9.pngFigure 41. Detailed Output Signal Waveforms