Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the driver input (D pin) to the differential outputs (CANH and CANL pins), plus the delay from the receiver inputs (CANH and CANL) to its output (R pin).
A typical loop delay for the SN65HVD230 transceiver is displayed in Figure 40. This loop delay will increase as the slope of the driver output is slowed during slope control mode. This increased loop delay means that there is a tradeoff between the total bus length able to be used and the driver's output slope used via the slope control pin of the device. For example, the loop delay for a 10-kΩ resistor from the RS pin to ground is ~100 ns, and the loop delay for a 100-kΩ resistor is ~500 ns. Therefore, if we use the following rule-of-thumb that the propagation delay of typical twisted pair bus cable is 5 ns/m, we can calculate an approximate cable length trade-off between normal high-speed mode and slope control mode with a 100-kΩ resistor. Using typical values, the loop delay for a recessive to dominant bit with RS tied directly to ground is 70ns, and with a 100-kΩ resistor is 535 ns. At 5ns/m of propagation delay, which you have to count in both directions the difference is 46.5 meters (535-70)/(2*5).
Another option to improving the elctromagnetic emissions of the device besides slowing down the edge rates of the driver in slope control mode is using quality shielded bus cabling.