SCES503J NOVEMBER   2003  – June 2015 SN74AUP1G57

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, CL = 5 pF
    7. 6.7  Switching Characteristics, CL = 10 pF
    8. 6.8  Switching Characteristics, CL = 15 pF
    9. 6.9  Switching Characteristics, CL = 30 pF
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Duration
    2. 7.2 Enable and Disable Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Logic Configurations
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Available in the Texas Instruments NanoStar™ Packages
  • Low Static-Power Consumption
    (ICC = 0.9 μA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5.3 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

2 Applications

  • Active Noise Cancellation (ANC)
  • Barcode Scanners
  • Blood Pressure Monitors
  • CPAP Machines
  • Cable Solutions
  • E-Books
  • Embedded PCs
  • Field Transmitter: Temperature or Pressure Sensors
  • HVAC: Heating, Ventilating, and Air Conditioning
  • Network-Attached Storage (NAS)
  • Server Motherboard and PSU
  • Software Defined Radio (SDR)
  • TV: High-Definition (HDTV), LCD, and Digital
  • Video Communications Systems

3 Description

The SN74AUP1G57 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All inputs can be connected to VCC or GND.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74AUP1G57YFP DSBGA (6) 1.16 x 0.76 mm
SN74AUP1G57YZP DSBGA (6) 1.388 x 0.888 mm
SN74AUP1G57DRY SON (6) 1.00 x 1.45 mm
SN74AUP1G57DSF SON (6) 1.00 x 1.00 mm
SN74AUP1G57DBV SOT-23 (6) 2.80 x 2.90 mm
SN74AUP1G57DCK SC70 (6) 2.10 x 2.00 mm
SN74AUP1G57DRL SOT (6) 1.60 x 1.60 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram (Positive Logic)

SN74AUP1G57 ld_ces503.gif