SCES582H July   2004  – April 2015 SN74AVCH2T45

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: VCCA = 1.2 V
    7. 7.7  Switching Characteristics: VCCA = 1.5 V
    8. 7.8  Switching Characteristics: VCCA = 1.8 V
    9. 7.9  Switching Characteristics: VCCA = 2.5 V
    10. 7.10 Switching Characteristics: VCCA = 3.3 V
    11. 7.11 Operating Characteristics
    12. 7.12 Typical Characteristics
      1. 7.12.1 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 1.8 V
      2. 7.12.2 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 2.5 V
      3. 7.12.3 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 3.3 V
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC Isolation
      2. 9.3.2 2-Rail Design
      3. 9.3.3 IO Ports are 4.6 V Tolerant
      4. 9.3.4 Partial Power Down Mode
      5. 9.3.5 Bus Hold on Data Inputs
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Unidirectional Logic Level-Shifting Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Bidirectional Logic Level-Shifting Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Enable Times
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DCU|8
  • YZP|8
  • DCT|8
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Available in the Texas Instruments NanoFree™ Package
  • VCC Isolation
  • 2-Rail Design
  • I/Os are 4.6 V Tolerant
  • Partial Power-Down-Mode Operation
  • Bus Hold on Data Inputs
  • Maximum Data Rates
    • 500 Mbps (1.8 V to 3.3 V)
    • 320 Mbps (< 1.8 V to 3.3 V)
    • 320 Mbps (Level-Shifting to 2.5 V or 1.8 V)
    • 280 Mbps (Level-Shifting to 1.5 V)
    • 240 Mbps (Level-Shifting to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22

2 Applications

  • Smartphone
  • Servers
  • Desktop PCs and Notebooks
  • Other Portable Devices

3 Description

This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B ports are designed to track VCCB and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation and level-shifting between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVCH2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The SN74AVCH2T45 features active bus-hold circuitry, which holds unused or un-driven inputs at a valid logic state. TI does not recommend using pull-up or pull-down resistors with the bus-hold circuitry.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74AVCH2T45 SSOP (8) 2.95 mm × 2.80 mm
VSSOP (8) 2.30 mm × 2.00 mm
DSBGA (8) 1.89 mm × 0.89 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN74AVCH2T45 ld_ces531.gif