SCES515L DECEMBER   2003  – February 2017 SN74LVC1T45

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics (VCCA = 1.8 V ± 0.15 V)
    7. 7.7  Switching Characteristics (VCCA = 2.5 V ± 0.2 V)
    8. 7.8  Switching Characteristics (VCCA = 3.3 V ± 0.3 V)
    9. 7.9  Switching Characteristics (VCCA = 5 V ±0.5 V)
    10. 7.10 Operating Characteristics
    11. 7.11 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
      2. 9.3.2 Support High Speed Translation
      3. 9.3.3 Ioff Supports Partial Power-Down Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Unidirectional Logic Level-Shifting Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Bidirectional Logic Level-Shifting Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Enable Times
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Features

  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ Package
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
  • VCC Isolation Feature – If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • DIR Input Circuit Referenced to VCCA
  • Low Power Consumption, 4-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
  • Max Data Rates
    • 420 Mbps (3.3-V to 5-V Translation)
    • 210 Mbps (Translate to 3.3 V)
    • 140 Mbps (Translate to 2.5 V)
    • 75 Mbps (Translate to 1.8 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Applications

  • Personal Electronic
  • Industrial
  • Enterprise
  • Telecom

Description

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry is always active on both A and B ports and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1T45DRLR SOT (6) 1.60 mm × 1.20 mm
SN74LVC1T45DBVR SOT-23 (6) 2.90 mm × 1.60 mm
SN74LVC1T45DCKR SC70 (6) 2.00 mm × 1.25 mm
SN74LVC1T45DPKR USON (6) 1.60 mm × 1.60 mm
SN74LVC1T45YZPR DSBGA (6) 1.39 mm × 0.90 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Functional Block Diagram

SN74LVC1T45 lo_ces515.gif