JAJSKZ9B December   2019  – March 2021 SN74LXCH8T245

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    7. 6.7  Switching Characteristics, VCCA = 1.5 ± 0.1 V
    8. 6.8  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    9. 6.9  Switching Characteristics, VCCA = 2.5 ± 0.2 V
    10. 6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    11. 6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V
    12. 6.12 Switching Characteristics: Tsk, TMAX
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 8.3.1.1 Control Inputs with Integrated Static Pull-Down Resistors
      2. 8.3.2  Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3  Partial Power Down (Ioff)
      4. 8.3.4  VCC Isolation and VCC Disconnect
      5. 8.3.5  Over-Voltage Tolerant Inputs
      6. 8.3.6  Glitch-Free Power Supply Sequencing
      7. 8.3.7  Negative Clamping Diodes
      8. 8.3.8  Fully Configurable Dual-Rail Design
      9. 8.3.9  Supports High-Speed Translation
      10. 8.3.10 Bus-Hold Data Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f = 1 MHz
  • ZO = 50 Ω
  • Δt/ΔV ≤ 1 ns/V

GUID-3D71EDC8-E56A-4C89-B036-A6A0F5521780-low.gif
A. CL includes probe and jig capacitance.
Figure 7-1 Load Circuit
Table 7-1 Load Circuit Conditions
Parameter VCCO RL CL S1 VTP
tpd Propagation (delay) time 1.1 V – 5.5 V 2 kΩ 15 pF Open N/A
ten, tdis Enable time or disable time 1.1 V – 1.6 V 2 kΩ 15 pF 2 × VCCO 0.1 V
1.65 V – 2.7 V 2 kΩ 15 pF 2 × VCCO 0.15 V
3.0 V – 5.5 V 2 kΩ 15 pF 2 × VCCO 0.3 V
ten, tdis Enable time or disable time 1.1 V – 1.6 V 2 kΩ 15 pF GND 0.1 V
1.65 V – 2.7 V 2 kΩ 15 pF GND 0.15 V
3.0 V – 5.5 V 2 kΩ 15 pF GND 0.3 V
GUID-9BC6F576-5C5E-45C5-9E0D-1F599105FC7C-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1.
Figure 7-2 Propagation Delay
GUID-76FAEEB1-24EC-4ECD-9E88-9F54DEED822D-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1.
Figure 7-3 Input Transition Rise and Fall Rate
GUID-7CFD1C67-6EBB-4B63-A71F-7B97DBE28FE3-low.gif
  1. Output waveform on the condition that input is driven to a valid Logic Low.
  2. Output waveform on the condition that input is driven to a valid Logic High.
  3. VCCO is the supply pin associated with the output port.
  4. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 7-4 Enable Time And Disable Time