JAJSDI7B July 2017 – October 2018 TAS2505-Q1
Audio data is transferred between the host processor and the TAS2505-Q1 via the digital audio data serial interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data options, support for I2S or PCM protocols, programmable data-length options, a TDM mode for multichannel operation, flexible master or slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly.
The audio bus of the TAS2505-Q1 can be configured for left- or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0, register 27, bits D5–D4. In addition, the word clock and bit clock can be independently configured in either master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected DAC sampling frequencies.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).