JAJSDI7B July   2017  – October 2018 TAS2505-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     ブロック概略図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  I2S/LJF/RJF Timing in Master Mode
    7. 6.7  I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  DSP Timing in Master Mode
    9. 6.9  DSP Timing in Slave Mode
    10. 6.10 I2C Interface Timing
    11. 6.11 SPI Interface Timing
    12. 6.12 Typical Characteristics
      1. 6.12.1 Class D Speaker Driver Performance
      2. 6.12.2 HP Driver Performance
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Audio Analog I/O
      2. 8.3.2 Audio DAC and Audio Analog Outputs
      3. 8.3.3 DAC
      4. 8.3.4 POR
      5. 8.3.5 CLOCK Generation and PLL
      6. 8.3.6 Speaker Driver
      7. 8.3.7 Automotive Diagnostics
    4. 8.4 Device Functional Modes
      1. 8.4.1 Digital Pins
      2. 8.4.2 Analog Pins
      3. 8.4.3 Multifunction Pins
      4. 8.4.4 Analog Signals
        1. 8.4.4.1 Analog Inputs AINL and AINR
      5. 8.4.5 DAC Processing Blocks — Overview
      6. 8.4.6 Digital Mixing and Routing
      7. 8.4.7 Analog Audio Routing
      8. 8.4.8 5V LDO
      9. 8.4.9 Digital Audio and Control Interface
        1. 8.4.9.1 Digital Audio Interface
        2. 8.4.9.2 Control Interface
          1. 8.4.9.2.1 I2C Control Mode
          2. 8.4.9.2.2 SPI Digital Interface
        3. 8.4.9.3 Device Special Functions
    5. 8.5 Register Map
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Circuit Configuration With Internal LDO
        1. 9.2.2.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Pad
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

Register Map

Table 4. Summary of Register Map

Decimal Hex DESCRIPTION
PAGE NO. REG. NO. PAGE NO. REG. NO.
0 0 0x00 0x00 Page Select Register
0 1 0x00 0x01 Software Reset Register
0 2 - 3 0x00 0x02 - 0x03 Reserved Registers
0 4 0x00 0x04 Clock Setting Register 1, Multiplexers
0 5 0x00 0x05 Clock Setting Register 2, PLL P and R Values
0 6 0x00 0x06 Clock Setting Register 3, PLL J Values
0 7 0x00 0x07 Clock Setting Register 4, PLL D Values (MSB)
0 8 0x00 0x08 Clock Setting Register 5, PLL D Values (LSB)
0 9 - 10 0x00 0x09 - 0x0A Reserved Registers
0 11 0x00 0x0B Clock Setting Register 6, NDAC Values
0 12 0x00 0x0C Clock Setting Register 7, MDAC Values
0 13 0x00 0x0D DAC OSR Setting Register 1, MSB Value
0 14 0x00 0x0E DAC OSR Setting Register 2, LSB Value
0 15 - 24 0x00 0x0F - 0x18 Reserved Registers
0 25 0x00 0x19 Clock Setting Register 10, Multiplexers
0 26 0x00 0x1A Clock Setting Register 11, CLKOUT M divider value
0 27 0x00 0x1B Audio Interface Setting Register 1
0 28 0x00 0x1C Audio Interface Setting Register 2, Data offset setting
0 29 0x00 0x1D Audio Interface Setting Register 3
0 30 0x00 0x1E Clock Setting Register 12, BCLK N Divider
0 31 0x00 0x1F Audio Interface Setting Register 4, Secondary Audio Interface
0 32 0x00 0x20 Audio Interface Setting Register 5
0 33 0x00 0x21 Audio Interface Setting Register 6
0 34 0x00 0x22 Reserved Register
0 35 - 36 0x00 0x23 - 0x24 Reserved Registers
0 37 0x00 0x25 DAC Flag Register 1
0 38 0x00 0x26 DAC Flag Register 2
0 39-41 0x00 0x27-0x29 Reserved Registers
0 42 0x00 0x2A Sticky Flag Register 1
0 43 0x00 0x2B Interrupt Flag Register 1
0 44 0x00 0x2C Sticky Flag Register 2
0 45 0x00 0x2D Reserved Register
0 46 0x00 0x2E Interrupt Flag Register 2
0 47 0x00 0x2F Reserved Register
0 48 0x00 0x30 INT1 Interrupt Control Register
0 49 0x00 0x31 INT2 Interrupt Control Register
0 50-51 0x00 0x32-0x33 Reserved Registers
0 52 0x00 0x34 GPIO/DOUT Control Register
0 53 0x00 0x35 DOUT Function Control Register
0 54 0x00 0x36 DIN Function Control Register
0 55 0x00 0x37 MISO Function Control Register
0 56 0x00 0x38 SCLK/DMDIN2 Function Control Register
0 57-59 0x00 0x39-0x3B Reserved Registers
0 60 0x00 0x3C DAC Instruction Set
0 61 - 62 0x00 0x3D -0x3E Reserved Registers
0 63 0x00 0x3F DAC Channel Setup Register 1
0 64 0x00 0x40 DAC Channel Setup Register 2
0 65 0x00 0x41 DAC Channel Digital Volume Control Register
0 66 - 80 0x00 0x42 - 0x50 Reserved Registers
0 81 0x00 0x51 Dig_Mic Control Register
0 82 - 127 0x00 0x52 - 0x7F Reserved Registers
1 0 0x01 0x00 Page Select Register
1 1 0x01 0x01 REF, POR and LDO BGAP Control Register
1 2 0x01 0x02 LDO Control Register
1 3 0x01 0x03 Playback Configuration Register 1
1 4 - 7 0x01 0x04 - 0x07 Reserved Registers
1 8 0x01 0x08 DAC PGA Control Register
1 9 0x01 0x09 Output Drivers, AINL, AINR, Control Register
1 10 0x01 0x0A Common Mode Control Register
1 11 0x01 0x0B HP Over Current Protection Configuration Register
1 12 0x01 0x0C HP Routing Selection Register
1 13 - 15 0x01 0x0D - 0x0F Reserved Registers
1 16 0x01 0x10 Reserved Registers
1 17 - 19 0x01 0x11 - 0x13 Reserved Registers
1 20 0x01 0x14 Reserved Registers
1 21 0x01 0x15 Reserved Register
1 22 0x01 0x16 Reserved Registers
1 23 0x01 0x17 Reserved Register
1 24 0x01 0x18 AINL Volume Control Register
1 25 0x01 0x19 AINR Volume Control Register
1 26 - 44 0x01 0x1A - 0x2C Reserved Registers
1 45 0x01 0x2D Speaker Amplifier Control 1
1 46 0x01 0x2E Speaker Volume Control Register
1 47 0x01 0x2F Reserved Register
1 48 0x01 0x30 Speaker Amplifier Volume Control 2
1 49 - 62 0x01 0x31 - 0x3E Right MICPGA Positive Terminal Input Routing Configuration Register
1 64 - 121 0x01 0x40 - 0x79 Reserved Registers
1 122 0x01 0x7A Reference Power Up Delay
1 123 - 127 0x01 0x7B - 0x7F Reserved Registers
2 - 43 0 - 127 0x02 - 0x2B 0x00 - 0x7F Reserved Registers
44 0 0x2C 0x00 Page Select Register
44 1 0x2C 0x01 DAC Adaptive Filter Configuration Register
44 2 - 7 0x2C 0x02 - 0x07 Reserved
44 8 - 127 0x2C 0x08 - 0x7F DAC Coefficients Buffer-A C(0:29)
45 - 52 0 0x2D-0x34 0x00 Page Select Register
45 - 52 1 - 7 0x2D-0x34 0x01 - 0x07 Reserved.
45 - 52 8 - 127 0x2D-0x34 0x08 - 0x7F DAC Coefficients Buffer-A C(30:255)
53 - 61 0 - 127 0x35 - 0x3D 0x00 - 0x7F Reserved Registers
62 - 70 0 0x3E-0x46 0x00 Page Select Register
62 - 70 1 - 7 0x3E-0x46 0x01 - 0x07 Reserved Registers
62 - 70 8 - 127 0x3E-0x46 0x08 - 0x7F DAC Coefficients Buffer-B C(0:255)
71 - 255 0 - 127 0x47 - 0x7F 0x00 - 0x7F Reserved Registers