JAJSDI7B July   2017  – October 2018 TAS2505-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     ブロック概略図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  I2S/LJF/RJF Timing in Master Mode
    7. 6.7  I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  DSP Timing in Master Mode
    9. 6.9  DSP Timing in Slave Mode
    10. 6.10 I2C Interface Timing
    11. 6.11 SPI Interface Timing
    12. 6.12 Typical Characteristics
      1. 6.12.1 Class D Speaker Driver Performance
      2. 6.12.2 HP Driver Performance
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Audio Analog I/O
      2. 8.3.2 Audio DAC and Audio Analog Outputs
      3. 8.3.3 DAC
      4. 8.3.4 POR
      5. 8.3.5 CLOCK Generation and PLL
      6. 8.3.6 Speaker Driver
      7. 8.3.7 Automotive Diagnostics
    4. 8.4 Device Functional Modes
      1. 8.4.1 Digital Pins
      2. 8.4.2 Analog Pins
      3. 8.4.3 Multifunction Pins
      4. 8.4.4 Analog Signals
        1. 8.4.4.1 Analog Inputs AINL and AINR
      5. 8.4.5 DAC Processing Blocks — Overview
      6. 8.4.6 Digital Mixing and Routing
      7. 8.4.7 Analog Audio Routing
      8. 8.4.8 5V LDO
      9. 8.4.9 Digital Audio and Control Interface
        1. 8.4.9.1 Digital Audio Interface
        2. 8.4.9.2 Control Interface
          1. 8.4.9.2.1 I2C Control Mode
          2. 8.4.9.2.2 SPI Digital Interface
        3. 8.4.9.3 Device Special Functions
    5. 8.5 Register Map
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Circuit Configuration With Internal LDO
        1. 9.2.2.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Pad
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

Power Supply Recommendations

The TAS2505-Q1 integrates a large amount of digital and analog functionality, and each of these blocks can be powered separately to enable the system to select appropriate power supplies for desired performance and power consumption. The device has separate power domains for digital IO, digital core, analog core, analog input and speaker drivers. If desired, all of the supplies (except for the supplies for speaker drivers, which can directly connect to the battery) can be connected together and be supplied from one source in the range of 1.65 to 1.95 V. Individually, the IOVDD voltage can be supplied in the range of 1.1 V to 3.6 V. For improved power efficiency, the digital core power supply can range from 1.26 V to 1.95 V. The analog core supply can either be derived from the internal LDO accepting an SPKVDD voltage in the range of 2.7 V to 5.5 V, or the AVDD pin can directly be driven with a voltage in the range of 1.5 V to 1.95 V. The speaker driver voltages (SPKVDD) can range from 2.7 V to 5.5 V.

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).