JAJSFI3A May 2018 – November 2018 TAS3251
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SREF | Reserved | SDSP | ||||
R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | Reserved | R/W | Reserved | |
4 | SREF | R/W | 0 | DSP clock source – This bit select the source clock for internal PLL. This bit is ignored and overriden in clock auto set mode.
0: The PLL reference clock is MCLK
|
3 | Reserved | R/W | Reserved | |
2-0 | SDSP | R/W | 0 | DAC clock source – These bits select the source clock for DSP clock divider.
000: Master clock (PLL/MCLK and OSC auto-select)
|