SCPS198C September 2014 – February 2017 TCA9534A
The TCA9534A is an 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 1.65-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most micro-controller families via the I2C interface (serial clock, SCL, and serial data, SDA, pins).
The TCA9534A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The INT pin can be connected to the interrupt input of a micro-controller. By sending an interrupt signal on this line, the remote I/O can inform the micro-controller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA9534A can remain a simple slave device. The device outputs (latched) have high-current drive capability for directly driving LEDs.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C slave address and allow up to eight devices to share the same I2C bus or SMBus.
The system master can reset the TCA9534A in the event of a timeout or other improper operation by cycling the power supply and causing a power-on reset (POR). A reset puts the registers in their default state and initializes the I2C /SMBus state machine.
The TCA9534A consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master.
The TCA9534A is identical to the TCA9554 except for the removal of the internal I/O pull-up resistors, which greatly reduces power consumption when the I/Os are held LOW.
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin must not exceed the recommended levels for proper operation.
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to VCC.
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9534A in a reset condition until VCC has reached VPORR. At that point, the reset condition is released and the TCA9534A registers and SMBus/I2C state machine initialize to their default states. After that, VCC must be lowered to below VPORF and then back up to the operating voltage for a power-on reset cycle.
The TCA9534A has a standard bidirectional I2C interface that is controlled by a master device in order to be configured or read the status of this device. Each slave on the I2C bus has a specific device address to differentiate between other slave devices that are on the same I2C bus. Many slave devices require configuration upon startup to set the behavior of the device. This is typically done when the master accesses internal register maps of the slave, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. For more information see the Understanding the I2C Bus application report.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I2C lines. For further details, see the I2C Pull-up Resistor Calculation application report. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition.
Table 1 shows the TCA9534A interface definition.
Figure 26 shows the address byte of the TCA9534A.
Table 2 shows the TCA9534A address reference.
|INPUTS||I2C BUS SLAVE ADDRESS|
|L||L||L||56 (decimal), 38 (hexadecimal)|
|L||L||H||57 (decimal), 39 (hexadecimal)|
|L||H||L||58 (decimal), 3A (hexadecimal)|
|L||H||H||59 (decimal), 3B (hexadecimal)|
|H||L||L||60 (decimal), 3C (hexadecimal)|
|H||L||H||61 (decimal), 3D (hexadecimal)|
|H||H||L||62 (decimal), 3E (hexadecimal)|
|H||H||H||63 (decimal), 3F (hexadecimal)|
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected, while a low (0) selects a write operation.
Following the successful Acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the TCA9534A (see Figure 27). Two bits of this command byte state the operation (read or write) and the internal register (input, output, polarity inversion or configuration) that is affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent.
Table 3 shows the TCA9534A command byte.
|CONTROL REGISTER BITS||COMMAND BYTE (HEX)||REGISTER||PROTOCOL||POWER-UP DEFAULT|
|0||0||0×00||Input Port||Read byte||XXXX XXXX|
|0||1||0×01||Output Port||Read/write byte||1111 1111|
|1||0||0×02||Polarity Inversion||Read/write byte||0000 0000|
|1||1||0×03||Configuration||Read/write byte||1111 1111|
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. See Table 4.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register is accessed next.
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See Table 5.
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin original polarity is retained. See Table 6.
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. See Table 7.
Data is exchanged between the master and the TCA9534A through write and read commands.
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master then sends the register address of the register to which it wishes to write. The slave acknowledges again, letting the master know it is ready. After this, the master starts sending the register data to the slave until the master has sent all the data necessary (which is sometimes only a single byte), and the master terminates the transmission with a STOP condition.
See Table 3 to see list of the internal registers and a description of each one.
Figure 28 shows an example of writing a single byte to a slave register.
Figure 29 shows an example of writing to the output port register.
Figure 30 shows an example of writing to the configuration or polarity inversion registers.
Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave, the master must first instruct the slave which register it wishes to read from. This is done by the master starting off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. When the slave acknowledges this register address, the master sends a START condition again, followed by the slave address with the R/W bit set to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data. At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the slave to halt communications and release the bus. The master follows this up with a STOP condition.
See Table 3 for the list of the internal registers and a description of each one.
If a read is requested by the master after a POR without first setting the command byte via a write, the device will NACK until a command byte-register address is set as described above.
Figure 31 shows an example of reading a single byte from a slave register.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. See Figure 32.