JAJSN80E August   2009  – May 2022 TCA9535

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V Tolerant I/O Ports
      2. 7.3.2 Hardware Address Pins
      3. 7.3.3 Interrupt ( INT) Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Powered-Up
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 Bus Transactions
          1. 7.5.1.1.1 Writes
          2. 7.5.1.1.2 Reads
      2. 7.5.2 Device Address
      3. 7.5.3 Control Register and Command Byte
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Calculating Junction Temperature and Power Dissipation
        2. 8.2.1.2 Minimizing ICC When I/O is Used to Control LED
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Power Supply Recommendations

In the event of a glitch or data corruption, TCA9535 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 9-1 and Figure 9-2.

GUID-9C69E0F5-EA7B-489D-ACEC-BE801281EC5D-low.gif Figure 9-1 VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
GUID-E7AE7CD3-86D2-4DA9-AF3F-FE27B8571D67-low.gif Figure 9-2 VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC

Table 9-1 specifies the performance of the power-on reset feature for TCA9535 for both types of power-on reset.

Table 9-1 Recommended Supply Sequencing And Ramp Rates
PARAMETER(1) MIN TYP MAX UNIT
VCC_FT Fall rate See Figure 9-1 0.1 ms
VCC_RT Rise rate See Figure 9-1 0.01 ms
VCC_TRR Time to re-ramp (when VCC drops to VVOR_MIN – 50 mV or when VCC drops to GND) See Figure 9-1 1 µs
VCC_GH The level (referenced to VCC) that VCC can glitch down to, but not cause a functional disruption when VCC_GW See Figure 9-3 1.2 V
VCC_MV

The minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated)

 See Figure 9-3 1.5 V
VCC_GW Glitch width that will not cause a functional disruption See Figure 9-3 10 μs
VPORF Voltage trip point of POR on falling VCC 0.75 1 1 V
VPORR Voltage trip point of POR on rising VCC 1.2 1.5 V
(1) TA = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 9-3 and Table 9-1 provide more information on how to measure these specifications.

GUID-21907428-460E-4DF3-ABFB-4B543E3BE922-low.gif Figure 9-3 Glitch Width And Glitch Height

VPORR is critical to the power-on reset. VPORR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 9-4 and Table 9-1 provide more details on this specification.

GUID-BB5C9265-29A6-464F-AE12-6466FC1F82EF-low.gif Figure 9-4 VPOR