JAJSN80E August   2009  – May 2022 TCA9535

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V Tolerant I/O Ports
      2. 7.3.2 Hardware Address Pins
      3. 7.3.3 Interrupt ( INT) Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Powered-Up
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 Bus Transactions
          1. 7.5.1.1.1 Writes
          2. 7.5.1.1.2 Reads
      2. 7.5.2 Device Address
      3. 7.5.3 Control Register and Command Byte
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Calculating Junction Temperature and Power Dissipation
        2. 8.2.1.2 Minimizing ICC When I/O is Used to Control LED
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-2)
MINMAXUNIT
I2C BUS—STANDARD MODE
fsclI2C clock frequency0100kHz
tschI2C clock high time4µs
tsclI2C clock low time4.7µs
tspI2C spike time50ns
tsdsI2C serial-data setup time250ns
tsdhI2C serial-data hold time0ns
ticrI2C input rise time1000ns
ticfI2C input fall time300ns
tocfI2C output fall time10-pF to 400-pF bus300ns
tbufI2C bus free time between stop and start4.7µs
tstsI2C start or repeated start condition setup4.7µs
tsthI2C start or repeated start condition hold4µs
tspsI2C stop condition setup4µs
tvd(data)Valid data timeSCL low to SDA output valid3.45µs
tvd(ack)Valid data time of ACK conditionACK signal from SCL low to
SDA (out) low		3.45µs
CbI2C bus capacitive load400pF
I2C BUS—FAST MODE
fsclI2C clock frequency0400kHz
tschI2C clock high time0.6µs
tsclI2C clock low time1.3µs
tspI2C spike time50ns
tsdsI2C serial-data setup time100ns
tsdhI2C serial-data hold time0ns
ticrI2C input rise time20300ns
ticfI2C input fall time20 × (VCC / 5.5 V)300ns
tocfI2C output fall time10-pF to 400-pF bus20 × (VCC / 5.5 V)300ns
tbufI2C bus free time between stop and start1.3µs
tstsI2C start or repeated start condition setup0.6µs
tsthI2C start or repeated start condition hold0.6µs
tspsI2C stop condition setup0.6µs
tvd(data)Valid data timeSCL low to SDA output valid0.9µs
tvd(ack)Valid data time of ACK conditionACK signal from SCL low to
SDA (out) low		0.9µs
CbI2C bus capacitive load400pF