JAJSI83G May   2012  – November 2019 TCA9548A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements
    7. 7.7 Reset Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 RESET Input
      2. 9.4.2 Power-On Reset
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
      2. 9.5.2 Device Address
      3. 9.5.3 Bus Transactions
        1. 9.5.3.1 Writes
        2. 9.5.3.2 Reads
      4. 9.5.4 Control Register
      5. 9.5.5 RESET Input
      6. 9.5.6 Power-On Reset
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-On Reset Requirements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.5.4 Control Register

Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the TCA9548A (see Figure 12). This register can be written and read via the I2C bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel. Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are received by the TCA9548A, it saves the last byte received.

TCA9548A cntrl_reg_cps207.gifFigure 12. Control Register

Table 2 shows the TCA9548A Command Byte Definition.

Table 2. Command Byte Definition

CONTROL REGISTER BITS COMMAND
B7 B6 B5 B4 B3 B2 B1 B0
X X X X X X X 0 Channel 0 disabled
1 Channel 0 enabled
X X X X X X 0 X Channel 1 disabled
1 Channel 1 enabled
X X X X X 0 X X Channel 2 disabled
1 Channel 2 enabled
X X X X 0 X X X Channel 3 disabled
1 Channel 3 enabled
X X X 0 X X X X Channel 4 disabled
1 Channel 4 enabled
X X 0 X X X X X Channel 5 disabled
1 Channel 5 enabled
X 0 X X X X X X Channel 6 disabled
1 Channel 6 enabled
0 X X X X X X X Channel 7 disabled
1 Channel 7 enabled
0 0 0 0 0 0 0 0 No channel selected, power-up/reset default state