JAJSH69B January   2018  – November 2019 TCAN4550-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図、MUC から CLKIN
      2.      概略回路図、水晶振動子
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  ESD Ratings, IEC ESD and ISO Transient Specification
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Supply Characteristics
    7. 7.7  Electrical Characteristics
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  VSUP Pin
      2. 9.3.2  VIO Pin
      3. 9.3.3  VCCOUT Pin
      4. 9.3.4  GND
      5. 9.3.5  INH Pin
      6. 9.3.6  WAKE Pin
      7. 9.3.7  FLTR Pin
      8. 9.3.8  RST Pin
      9. 9.3.9  OSC1 and OSC2 Pins
      10. 9.3.10 nWKRQ Pin
      11. 9.3.11 nINT Interrupt Pin
      12. 9.3.12 GPIO1 Pin
      13. 9.3.13 GPO2 Pin
      14. 9.3.14 CANH and CANL Bus Pins
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Sleep Mode
        1. 9.4.3.1 Bus Wake via RXD_INT Request (BWRR) in Sleep Mode
        2. 9.4.3.2 Local Wake Up (LWU) via WAKE Input Terminal
      4. 9.4.4 Test Mode
      5. 9.4.5 Failsafe Feature
      6. 9.4.6 Protection Features
        1. 9.4.6.1 Watchdog Function
        2. 9.4.6.2 Driver and Receiver Function
        3. 9.4.6.3 Floating Terminals
        4. 9.4.6.4 TXD_INT Dominant Timeout (DTO)
        5. 9.4.6.5 CAN Bus Short Circuit Current Limiting
        6. 9.4.6.6 Thermal Shutdown
        7. 9.4.6.7 Under Voltage Lockout (UVLO) and Unpowered Device
          1. 9.4.6.7.1 UVSUP and UVCCOUT
          2. 9.4.6.7.2 UVIO
          3. 9.4.6.7.3 Fault and M_CAN Core Behavior:
      7. 9.4.7 CAN FD
    5. 9.5 Programming
      1. 9.5.1 SPI Communication
        1. 9.5.1.1 Chip Select Not (nCS):
        2. 9.5.1.2 SPI Clock Input (SCLK):
        3. 9.5.1.3 SPI Data Input (SDI):
        4. 9.5.1.4 SPI Data Output (SDO):
      2. 9.5.2 Register Descriptions
    6. 9.6 Register Maps
      1. 9.6.1 Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F
        1. 9.6.1.1 DEVICE_ID1[31:0] (address = h0000) [reset = h4E414354]
          1. Table 10. Device ID Field Descriptions
        2. 9.6.1.2 DEVICE_ID2[31:0] (address = h0004) [reset = h30353534]
          1. Table 11. Device ID Field Descriptions
        3. 9.6.1.3 Revision (address = h0008) [reset = h00110201]
          1. Table 12. Revision Field Descriptions
        4. 9.6.1.4 Status (address = h000C) [reset = h0000000U]
          1. Table 13. Status Field Descriptions
      2. 9.6.2 Device Configuration Registers: 16'h0800 to 16'h08FF
        1. 9.6.2.1 Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000468]
          1. Table 15. Modes of Operation and Pin Configuration Registers Field Descriptions
        2. 9.6.2.2 Timestamp Prescalar (address = h0804) [reset = h00000002]
          1. Table 16. EMC Enhancement and Timestamp Prescalar Field Descriptions
        3. 9.6.2.3 Test Register and Scratch Pad (address = h0808) [reset = h00000000]
          1. Table 17. Test and Scratch Pad Register Field Descriptions
        4. 9.6.2.4 Test Register (address = h080C) [reset = h00000000]
          1. Table 18. Test Register Field Descriptions
      3. 9.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830
        1. 9.6.3.1 Interrupts (address = h0820) [reset = h00100000]
          1. Table 19. Interrupts Field Descriptions
        2. 9.6.3.2 MCAN Interrupts (address = h0824) [reset = h00000000]
          1. Table 20. MCAN Interrupts Field Descriptions
        3. 9.6.3.3 Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]
          1. Table 21. Interrupt Enables Field Descriptions
      4. 9.6.4 CAN FD Register Set: 16'h1000 to 16'h10FF
        1. 9.6.4.1  Core Release Register (address = h1000) [reset = hrrrddddd]
          1. Table 25. Core Release Register Field Descriptions
        2. 9.6.4.2  Endian Register (address = h1004) [reset = h87654321]
          1. Table 26. Endian Register Field Descriptions
        3. 9.6.4.3  Customer Register (address = h1008) [reset = h00000000]
          1. Table 27. Customer Register Field Descriptions
        4. 9.6.4.4  Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]
          1. Table 28. Data Bit Timing & Prescaler Field Descriptions
        5. 9.6.4.5  Test Register (address = h1010 ) [reset = h00000000]
          1. Table 29. Test Register Field Descriptions
        6. 9.6.4.6  RAM Watchdog (address = h1014) [reset = h00000000]
          1. Table 30. RAM Watchdog Field Descriptions
        7. 9.6.4.7  Control Register (address = h1018) [reset = 0000 0019]
          1. Table 31. Control Register Field Descriptions
        8. 9.6.4.8  Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]
          1. Table 32. Nominal Bit Timing & Prescaler Register Field Descriptions
        9. 9.6.4.9  Timestamp Counter Configuration (address = h1020) [reset = h00000000]
          1. Table 33. Timestamp Counter Configuration Descriptions
        10. 9.6.4.10 Timestamp Counter Value (address = h1024) [reset = h00000000]
          1. Table 34. Timestamp Counter Value Field Descriptions
        11. 9.6.4.11 Timeout Counter Configuration (address = h1028) [reset = hFFFF0000]
          1. Table 35. Timeout Counter Configuration Field Descriptions
        12. 9.6.4.12 Timeout Counter Value (address = h102C) [reset = h0000FFFF]
          1. Table 36. Timeout Counter Value Field Descriptions
        13. 9.6.4.13 Reserved (address = h1030 - h103C) [reset = h00000000]
          1. Table 37. Reserved Field Descriptions
        14. 9.6.4.14 Error Counter Register (address = h1040) [reset = h00000000]
          1. Table 38. Error Counter Register Field Descriptions
        15. 9.6.4.15 Protocol Status Register (address = h1044) [reset = h00000707]
          1. Table 39. Protocol Status Register Field Descriptions
        16. 9.6.4.16 Transmitter Delay Compensation Register (address = h1048) [reset = h00000000]
          1. Table 40. Transmitter Delay Compensation Register Field Descriptions
        17. 9.6.4.17 Reserved (address = h104C) [reset = h00000000]
          1. Table 41. Reserved Field Descriptions
        18. 9.6.4.18 Interrupt Register (address = h1050) [reset = h00000000]
          1. Table 42. Interrupt Register Field Descriptions
        19. 9.6.4.19 Interrupt Enable (address = h1054) [reset = h00000000]
          1. Table 43. Interrupt Enable Field Descriptions
        20. 9.6.4.20 Interrupt Line Select (address = h1058) [reset = h00000000]
          1. Table 44. Interrupt Line Select Field Descriptions
        21. 9.6.4.21 Interrupt Line Enable (address = h105C) [reset = h00000000]
          1. Table 45. Interrupt Line Enable Field Descriptions
        22. 9.6.4.22 Reserved (address = h1060 - h107C) [reset = h00000000]
          1. Table 46. Reserved Field Descriptions
        23. 9.6.4.23 Global Filter Configuration (address = h1080) [reset = h00000000]
          1. Table 47. Global Filter Configuration Field Descriptions
        24. 9.6.4.24 Standard ID Filter Configuration (address = h1084) [reset = h00000000]
          1. Table 48. Standard ID Filter Configuration Field Descriptions
        25. 9.6.4.25 Extended ID Filter Configuration (address = h1088) [reset = h00000000]
          1. Table 49. Extended ID Filter Configuration Field Descriptions
        26. 9.6.4.26 Reserved (address = h108C) [reset = h00000000]
          1. Table 50. Reserved Field Descriptions
        27. 9.6.4.27 Extended ID AND Mask (address = h1090) [reset = h1FFFFFFF]
          1. Table 51. Extended ID AND Mask Field Descriptions
        28. 9.6.4.28 High Priority Message Status (address = h1094) [reset = h00000000]
          1. Table 52. High Priority Message Status Field Descriptions
        29. 9.6.4.29 New Data 1 (address = h1098) [reset = h00000000]
          1. Table 53. New Data 1 Field Descriptions
        30. 9.6.4.30 New Data 2 (address = h109C) [reset = h00000000]
          1. Table 54. New Data 2 Field Descriptions
        31. 9.6.4.31 Rx FIFO 0 Configuration (address = h10A0) [reset = h00000000]
          1. Table 55. Rx FIFO 0 Configuration Field Descriptions
        32. 9.6.4.32 Rx FIFO 0 Status (address = h10A4) [reset = h00000000]
          1. Table 56. Rx FIFO 0 Status Field Descriptions
        33. 9.6.4.33 Rx FIFO 0 Acknowledge (address = h10A8) [reset = h00000000]
          1. Table 57. Rx FIFO 0 Acknowledge Field Descriptions
        34. 9.6.4.34 Rx Buffer Configuration (address = h10AC) [reset = h00000000]
          1. Table 58. Rx Buffer Configuration Field Descriptions
        35. 9.6.4.35 Rx FIFO 1 Configuration (address = h10B0) [reset = h00000000]
          1. Table 59. Rx FIFO 1 Configuration Field Descriptions
        36. 9.6.4.36 Rx FIFO 1 Status (address = h10B4) [reset = h00000000]
          1. Table 60. Rx FIFO 1 Status Field Descriptions
        37. 9.6.4.37 Rx FIFO 1 Acknowledge (address = h10B8) [reset = h00000000]
          1. Table 61. Rx FIFO 1 Acknowledge Field Descriptions
        38. 9.6.4.38 Rx Buffer/FIFO Element Size Configuration (address = h10BC) [reset = h00000000]
          1. Table 62. Rx Buffer/FIFO Element Size Configuration Field Descriptions
        39. 9.6.4.39 Tx Buffer Configuration (address = h10C0) [reset = h00000000]
          1. Table 63. Tx Buffer Configuration Field Descriptions
        40. 9.6.4.40 Tx FIFO/Queue Status (address = h10C4) [reset = h00000000]
          1. Table 64. Tx FIFO/Queue Status Field Descriptions
        41. 9.6.4.41 Tx Buffer Element Size Configuration (address = h10C8) [reset = h00000000]
          1. Table 65. Tx Buffer Element Size Configuration Field Descriptions
        42. 9.6.4.42 Tx Buffer Request Pending (address = h10CC) [reset = h00000000]
          1. Table 66. Tx Buffer Request Pending Field Descriptions
        43. 9.6.4.43 Tx Buffer Add Request (address = h10D0) [reset = h00000000]
          1. Table 67.   Tx Buffer Add Request Field Descriptions
          2. 9.6.4.43.1  Tx Buffer Cancellation Request (address = h10D4 [reset = h00000000]
            1. Table 68. Tx Buffer Cancellation Request Field Descriptions
          3. 9.6.4.43.2  Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]
            1. Table 69. Tx Buffer Add Request Transmission Occurred Field Descriptions
          4. 9.6.4.43.3  Tx Buffer Cancellation Finished (address = h10DC) [reset = h00000000]
            1. Table 70. Tx Buffer Cancellation Finished Field Descriptions
          5. 9.6.4.43.4  Tx Buffer Transmission Interrupt Enable (address = h10E0) [reset = h00000000]
            1. Table 71. Tx Buffer Transmission Interrupt Enable Field Descriptions
          6. 9.6.4.43.5  Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]
            1. Table 72. Tx Buffer Cancellation Finished Interrupt Enable Field Descriptions
          7. 9.6.4.43.6  Reserved (address = h10E8) [reset = h00000000]
            1. Table 73. Reserved Field Descriptions
          8. 9.6.4.43.7  Reserved (address = h10EC) [reset = h00000000]
            1. Table 74. Reserved Field Descriptions
          9. 9.6.4.43.8  Tx Event FIFO Configuration (address = h10F0) [reset = h00000000]
            1. Table 75. Tx Event FIFO Configuration Field Descriptions
          10. 9.6.4.43.9  Tx Event FIFO Status (address = h10F4) [reset = h00000000]
            1. Table 76. Tx Event FIFO Status Field Descriptions
          11. 9.6.4.43.10 Tx Event FIFO Acknowledge (address = h10F8) [reset = h00000000]
            1. Table 77. Tx Event FIFO Acknowledge Field Descriptions
          12. 9.6.4.43.11 Reserved (address = h10FC) [reset = h00000000]
            1. Table 78. Reserved Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Design Consideration
      1. 10.1.1 Crystal and Clock Input Requirements
      2. 10.1.2 Bus Loading, Length and Number of Nodes
      3. 10.1.3 CAN Termination
        1. 10.1.3.1 Termination
        2. 10.1.3.2 CAN Bus Biasing
      4. 10.1.4 INH Brownout Behavior
    2. 10.2 Typical Application
      1. 10.2.1 Detailed Requirements
      2. 10.2.2 Detailed Design Procedures
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
        1. 13.1.1.1 CAN トランシーバの物理層の標準
        2. 13.1.1.2 EMC要件
        3. 13.1.1.3 準拠テストの要件
        4. 13.1.1.4 サポート・ドキュメント
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

CAN FD Register Set: 16'h1000 to 16'h10FF

The following tables provide the CAN FD programming register sets starting at 16'h1000.

The MRAM and start address for the following registers has special consideration:

  • SIDFC (0x1084)
  • XIDFC (0x1088)
  • RXF0C (0x10A0)
  • RXF1C (0x10B0)
  • TXBC (0x10C0)
  • TXEFC (0x10F0)

The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a write to ensure this behavior.

When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired start address is 0x8634, then bits SA[15:0] will be 0x0634.

Table 22. Legend

Code Description
R Read
C Clear on Write
d date
n Value after Reset
p Protected Set
P Protected Write
r Release
S Set on Read
t Test Value
U Undefined
W Write
X Reset on Read

Table 23. CAN FD Register Set

ADDRESS SYMBOL NAME RESET ACC
1000 CREL Core Release Register rrrd dddd R
1004 ENDN Endian Register 8765 4321 R
1008 CUST Customer Register 0000 0000 R
100C DBTP Data Bit Timing & Prescaler Register 0000 0A33 RP
1010 TEST Test Register 0000 0000 RP
1014 RWD RAM Watchdog 0000 0000 RP
1018 CCCR CC Control Register 0000 0019 RWPp
101C NBTP Nominal Bit Timing & Prescaler Register 0600 0A03 RP
1020 TSCC Timestamp Counter Configuration 0000 0000 RP
1024 TSCV Timestamp Counter Value 0000 0000 RC
1028 TOCC Timeout Counter Configuration FFFF 0000 RP
102C TOCV Timeout Counter Value 0000 FFFF RC
1030 RSVD Reserved 0000 0000 R
1034 RSVD Reserved 0000 0000 R
1038 RSVD Reserved 0000 0000 R
103C RSVD Reserved 0000 0000 R
1040 ECR Error Counter Register 0000 0000 RX
1044 PSR Protocol Status Register 0000 0707 RXS
1048 TDCR Transmitter Delay Compensation Register 0000 0000 RP
104C RSVD Reserved 0000 0000 R
1050 IR Interrupt Register 0000 0000 RW
1054 IE Interrupt Enable 0000 0000 RW
1058 ILS Interrupt Line Select 0000 0000 RW
105C ILE Interrupt Line Enable 0000 0000 RW
1060 RSVD Reserved 0000 0000 R
1064 RSVD Reserved 0000 0000 R
1068 RSVD Reserved 0000 0000 R
106C RSVD Reserved 0000 0000 R
1070 RSVD Reserved 0000 0000 R
1074 RSVD Reserved 0000 0000 R
1078 RSVD Reserved 0000 0000 R
107C RSVD Reserved 0000 0000 R
1080 GFC Global Filter Configuration 0000 0000 RP
1084 SIDFC Standard ID Filter Configuration 0000 0000 RP
1088 XIDFC Extended ID Filter Configuration 0000 0000 RP
108C RSVD Reserved 0000 0000 R
1090 XIDAM Extended ID and MASK 1FFF FFFF RP
1094 HPMS High Priority Message Status 0000 0000 R
1098 NDAT1 New Data 1 0000 0000 RW
109C NDAT2 New Data 2 0000 0000 RW
10A0 RXF0C Rx FIFO 0 Configuration 0000 0000 RP
10A4 RXF0S Rx FIFO 0 Status 0000 0000 R
10A8 RXF0A Rx FIFO 0 Acknowledge 0000 0000 RW
10AC RXBC Rx Buffer Configuration 0000 0000 RP
10B0 RXF1C Rx FIFO 1 Configuration 0000 0000 RP
10B4 RXF1S Rx FIFO 1 Status 0000 0000 R
10B8 RXF1A Rx FIFO 1 Acknowledge 0000 0000 RW
10BC RXESC Rx Buffer/FIFO Element Size Configuration 0000 0000 RP
10C0 TXBC Tx Buffer Configuration 0000 0000 RP
10C4 TXFQS Tx FIFO/Queue Status 0000 0000 R
10C8 TXESC Tx Buffer Element Size Configuration 0000 0000 RP
10CC TXBRP Tx Buffer Request Pending 0000 0000 R
10D0 TXBAR Tx Buffer Add Request 0000 0000 RW
10D4 TXBCR Tx Buffer Cancellation Request 0000 0000 RW
10D8 TXBTO Tx Buffer Transmission Occurred 0000 0000 R
10DC TXBCF Tx Buffer Cancellation Finished 0000 0000 R
10E0 TXBTIE Tx Buffer Transmission Interrupt Enable 0000 0000 RW
10E4 TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0000 0000 RW
10E8 RSVD Reserved 0000 0000 R
10EC RSVD Reserved 0000 0000 R
10F0 TXEFC Tx Event FIFO Configuration 0000 0000 RP
10F4 TXEFS Tx Event FIFO Status 0000 0000 R
10F8 TXEFA Tx Event FIFO Acknowledge 0000 0000 RW
10FC RSVD Reserved 0000 0000 R

Table 24. CAN FD Register Set Description

Offset Name Bit Pos. MSB LSB Access
1000 CREL 7:0 Day[7:0] (two digit, BCD-Coded) R
15:8 Month[15:8] (two digit, BCD-Coded) R
23:16 SUBSTEP[7:4] (One digit, BCD-Coded) Year[3:0] (one digit, BCD-Coded) R
31:24 REL[7:4] (One digit, BCD-Coded) STEP[3:0] (one digit, BCD-Coded) R
1004 ENDN 7:0 ETV[7:0] (Endianness Test Value) R
15:8 ETV[15:8] (Endianness Test Value) R
23:16 ETV[23:16] (Endianness Test Value) R
31:24 ETV[31:24] (Endianness Test Value) R
1008 CUST 7:0
15:8
23:16
31:24
100C DBTP 7:0 DTSEG2(Data Time Seg before Sample Point) DSJW (Data (Re)Synchronization Jump Width) RP
15:8 Reserved DTSEG1(Data Time Seg before Sample Point) RP
23:16 TDC Reserved DBRP (Data Bit Rate Prescaler) RP
31:24 Reserved R
1010 TEST 7:0 RX TX LBCK Reserved RP-U
15:8 Reserved R
23:16 Reserved R
31:24 Reserved R
1014 RWD 7:0 WDC (Watchdog Configuration) RP
15:8 WDV (Watchdog Counter Value) R
23:16 Reserved R
31:24 Reserved R
1018 CCCR 7:0 TEST DAR MON CSR CSA ASM CCE INIT RWp
15:8 NISO TXP EFBI PXHD Reserved BRSE FDOE RP
23:16 Reserved R
31:24 Reserved R
101C NBTP 7:0 Reserved NTSEG2 (Nominal time Segment After Sample Point) RP
15:8 NTSEG1 (Nominal Time Segment Before Sample Point) RP
23:16 NBRP[7:0] (Nominal Bit Rate Prescaler) RP
31:24 NSJW[6;0] (Nominal (RE)Synchronization Jump Width) NBRP[8] RP
1020 TSCC 7:0 Reserved TSS[1:0] Timestamp Select RP
15:8 Reserved R
23:16 Reserved TCP (Timestamp Counter Prescaler) RP
31:24 Reserved R
1024 TSCV 7:0 TSC[15:0] (Timestamp Counter) RC
15:8 RC
23:16 Reserved R
31:24 Reserved R
1028 TOCC 7:0 Reserved TOS (Timeout SEL) ETOC RP
15:8 Reserved R
23:16 TOP[15:0] (Timeout Period) RP
31:24 RP
102C TOCV 7:0 TOC[15:0] (Timeout Counter) RC
15:8 RC
23:16 Reserved R
31:24 Reserved R
1030 – 103C RSVD 31:0 Reserved R
1040 ECR 7:0 TEC (Transmit Error Counter) R
15:8 REC (Receive Error Counter) R
23:16 CEL (CAN Error Logging) X
31:24 Reserved R
1044 PSR 7:0 BO EW EP ACT (Activity) LEC (Last Error Code) RS
15:8 Reserved PXE RFDF RBRS RESI DLEC ( Data Phase Last Error Code) RSX
23:16 Reserved TDCV[6:0] (Transmitter Delay Compensation Value) R
31:24 Reserved R
1048 TDCR 7:0 Reserved TDCF (Transmitter Delay Compensation Filter Window Length) RP
15:8 Reserved TDCO (Transmitter Delay Compensation Offset) RP
23:16 Reserved R
31:24 Reserved R
104C RSVD 31:0 Reserved R
1050 IR 7:0 RF1L RF1F RF1W RF1N RF0L RF0F RF0W RF0N R/W
15:8 TEFL TEFF TEFW TEFN TFE TCF TC HPM R/W
23:16 EP ELO BEU BEC DRX TOO MRAF TSW R/W
31:24 Reserved ARA PED PEA WDI BO EW R/W
1054 IE 7:0 RF1LE RF1FE RF1WE RF1NE RF0LE RF0FE RF0WE RF0NE R/W
15:8 TEFLE TEFFE TEFWE TEFNE TFEE TCFE TCE HPME R/W
23:16 EPE ELOE BEUE BECE DRXE TOOE MRAFE TSWE R/W
31:24 Reserved ARAE PEDE PEAE WDIE BOE EWE R/W
1058 ILS 7:0 RF1LL RF1FL RF1WL RF1NL RF0LL RF0FL RF0WL RF0NL R/W
15:8 TEFLL TEFFL TEFWL TEFNL TFEL TCFL TCL HPML R/W
23:16 EPL ELOL BEUL BECL DRXL TOOL MRAFL TSWL R/W
31:24 Reserved ARAL PEDL PEAL WDIL BOL EWL R/W
105C ILE 7:0 Reserved EINT1 EINT0 R/W
15:8 Reserved R
23:16 Reserved R
31:24 Reserved R
1060 – 107C RSVD 31:0 Reserved R
1080 GFC 7:0 Reserved ANFS ANFE RRFS RRFE RP
15:8 Reserved R
23:16 Reserved R
31:24 Reserved R
1084 SIDFC 7:0 FLSS[7:2] (Filter List Standard Start Address) Reserved RP
15:8 FLSS[15:8] (Filter List Standard Start Address) RP
23:16 LSS (List Size Standard) RP
31:24 Reserved R
1088 XIDFC 7:0 FLESA[7:2] (Filter List Extended Start Address) Reserved RP
15:8 FLESA[15:8] (Filter List Extended Start Address) RP
23:16 Reserved LSE (List Size Extended) RP
31:24 Reserved R
108C RSVD 31:0 Reserved R
1090 XIDAM 7:0 EIDM[7:0] (Extended ID AND MASK) RP
15:8 EIDM[15:8] (Extended ID AND MASK) RP
23:16 EIDM[23:16] (Extended ID AND MASK) RP
31:24 Reserved EIDM[28:24] (Extended ID AND MASK) RP
1094 HPMS 7:0 MSI (Message Storage Index) BIDX (Buffer Index) R
15:8 FLST FIDX (Filter Index) R
23:16 Reserved R
31:24 Reserved R
1098 NDAT1 7:0 ND7 ND6 ND5 ND4 ND3 ND2 ND1 ND0 R/W
15:8 ND15 ND14 ND13 ND12 ND11 ND10 ND9 ND8 R/W
23:16 ND23 ND22 ND21 ND20 ND19 ND18 ND17 ND16 R/W
31:24 ND31 ND30 ND29 ND28 ND27 ND26 ND25 ND24 R/W
109C NDAT2 7:0 ND39 ND38 ND37 ND36 ND35 ND34 ND33 ND32 R/W
15:8 ND47 ND46 ND45 ND44 ND43 ND42 ND41 ND40 R/W
23:16 ND55 ND54 ND53 ND52 ND51 ND50 ND49 ND48 R/W
31:24 ND63 ND62 ND61 ND60 ND59 ND58 ND57 ND56 R/W
10A0 RXF0C 7:0 F0SA[7:2] (RX FIFO 0 Start Address) Reserved RP
15:8 F0SA[15:8] (RX FIFO 0 Start Address) RP
23:16 Reserved F0S (RX FIFO 0 Size) RP
31:24 F0OM F0WM (RX FIFO 0 Watermark) RP
10A4 RXF0S 7:0 Reserved R
15:8 Reserved R
23:16 Reserved R
31:24 Reserved R
10A8 RXF0A 7:0 Reserved F0A (RX FIFO 0 Acknowledge Index) R/W
15:8 Reserved R
23:16 Reserved R
31:24 Reserved R
10AC RXBC 7:0 RBSA[7:2] (RX Buffer Configuration) Reserved RP
15:8 RBSA[15:8] (RX Buffer Configuration) RP
23:16 Reserved R
31:24 Reserved R
10B0 RXF1C 7:0 F1SA[7:2] (RX FIFO 1 Start Address) Reserved RP
15:8 F1SA[15:8] (RX FIFO 1 Start Address) RP
23:16 Reserved F1S (RX FIFO 1 Size) RP
31:24 F1OM F1WM (RX FIFO 1 Watermark) RP
10B4 RXF1S 7:0 Reserved F1FL (RX FIFO 1 Fill Level) R
15:8 Reserved F1GI (RX FIFO 1 Get Index) R
23:16 Reserved F1PI (RX FIFO 1 Put Index) R
31:24 DMS (Data Message Status) Reserved RF1L F1F R
10B8 RXF1A 7:0 Reserved F1AI (RX FIFO 1 Acknowledge Index) R/W
15:8 Reserved R
23:16 Reserved R
31:24 Reserved R
10BC RXESC 7:0 Reserved F1DS (RX FIFO 1 Data Field Size) Reserved F0DS (RX FIFO 0 Data Field Size) RP
15:8 Reserved RBDS (RX Buffer Data Field Size) RP
23:16 Reserved R
31:24 Reserved R
10C0 TXBC 7:0 TBSA[7:2] (TX Buffer Start Address) Reserved RP
15:8 TBSA[15:8] (TX Buffer Start Address) RP
23:16 Reserved NDTB (Number of Dedicated Transmit Buffers) RP
31:24 Reserved TFQM TFQS (Transmit FIFO/Queue Size) RP
10C4 TXQFS 7:0 Reserved TFFL (TX FIFO Free Level) R
15:8 Reserved TFGI (TX FIFO Get Index) R
23:16 Reserved TFQF TFQP (TX FIFO/Queue Put Index) R
31:24 Reserved R
10C8 TXESC 7:0 Reserved TBDS (TX Buffer Data Field Size) RP
15:8 Reserved R
23:16 Reserved R
31:24 Reserved R
10CC TXBRP 7:0 TRP7 TRP6 TRP5 TRP4 TRP3 TRP2 TRP1 TRP0 R
15:8 TRP15 TRP14 TRP13 TRP12 TRP11 TRP10 TRP9 TRP8 R
23:16 TRP23 TRP22 TRP21 TRP20 TRP19 TRP18 TRP17 TRP16 R
31:24 TRP31 TRP30 TRP29 TRP28 TRP27 TRP26 TRP25 TRP24 R
10D0 TXBAR 7:0 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 R/W
15:8 AR15 AR14 AR13 AR12 AR11 AR10 AR9 AR8 R/W
23:16 AR23 AR22 AR21 AR20 AR19 AR18 AR17 AR16 R/W
31:24 AR31 AR30 AR29 AR28 AR27 AR26 AR25 AR24 R/W
10D4 TXBCR 7:0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 RW
15:8 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 RW
23:16 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 RW
31:24 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 RW
10D8 TXBTO 7:0 TO7 TO6 TO5 TO4 TO3 TO2 TO1 TO0 R
15:8 TO15 TO14 TO13 TO12 TO11 TO10 TO9 TO8 R
23:16 TO23 TO22 TO21 TO20 TO19 TO18 TO17 TO16 R
31:24 TO31 TO30 TO29 TO28 TO27 TO26 TO25 TO24 R
10DC TXBCF 7:0 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 R
15:8 CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 R
23:16 CF23 CF22 CF21 CF20 CF19 CF18 CF17 CF16 R
31:24 CF31 CF30 CF29 CF28 CF27 CF26 CF25 CF24 R
10E0 TXBTIE 7:0 TIE7 TIE6 TIE5 TIE4 TIE3 TIE2 TIE1 TIE0 RW
15:8 TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8 RW
23:16 TIE23 TIE22 TIE21 TIE20 TIE19 TIE18 TIE17 TIE16 RW
31:24 TIE31 TIE30 TIE29 TIE28 TIE27 TIE26 TIE25 TIE24 RW
10E4 TXBCIE 7:0 CFIE7 CFIE6 CFIE5 CFIE4 CFIE3 CFIE2 CFIE1 CFIE0 RW
15:8 CFIE15 CFIE14 CFIE13 CFIE12 CFIE11 CFIE10 CFIE9 CFIE8 RW
23:16 CFIE23 CFIE22 CFIE21 CFIE20 CFIE19 CFIE18 CFIE17 CFIE16 RW
31:24 CFIE31 CFIE30 CFIE29 CFIE28 CFIE27 CFIE26 CFIE25 CFIE24 RW
10E8 - 10EC RSVD 31:0 Reserved R
10F0 TXEFC 7:0 EFSA[7:2] (Event FIFO Start Address) Reserved RP
15:8 EFSA[15:8] (Event FIFO Start Address) RP
23:16 Reserved EFS (Event FIFO Size) RP
31:24 Reserved EFWM (Event FIFO Watermark) RP
10F4 TXEFS 7:0 Reserved EFFL (Event FIFO Fill Level)
15:8 Reserved EFGI (Event FIFO Get Index)
23:16 Reserved EFPI (Event FIFO Put Index)
31:24 Reserved TEFL EFF R
10F8 TXEFA 7:0 Reserved EFA (Event FIFO Acknowledge Index) RW
15:8 Reserved R
23:16 Reserved R
31:24 Reserved R
10FC RSVD 31:0 Reserved R