JAJSGQ7A December   2018  – January 2020 TCAN4550

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図、MUC から CLKIN
      2.      概略回路図、水晶振動子
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  ESD Ratings, IEC ESD and ISO Transient Specification
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Supply Characteristics
    7. 7.7  Electrical Characteristics
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  VSUP Pin
      2. 9.3.2  VIO Pin
      3. 9.3.3  VCCOUT Pin
      4. 9.3.4  GND
      5. 9.3.5  INH Pin
      6. 9.3.6  WAKE Pin
      7. 9.3.7  FLTR Pin
      8. 9.3.8  RST Pin
      9. 9.3.9  OSC1 and OSC2 Pins
      10. 9.3.10 nWKRQ Pin
      11. 9.3.11 nINT Interrupt Pin
      12. 9.3.12 GPO1 Pin
      13. 9.3.13 GPO2 Pin
      14. 9.3.14 CANH and CANL Bus Pins
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Sleep Mode
        1. 9.4.3.1 Bus Wake via RXD_INT Request (BWRR) in Sleep Mode
        2. 9.4.3.2 Local Wake Up (LWU) via WAKE Input Terminal
      4. 9.4.4 Test Mode
      5. 9.4.5 Failsafe Feature
      6. 9.4.6 Protection Features
        1. 9.4.6.1 Watchdog Function
        2. 9.4.6.2 Driver and Receiver Function
        3. 9.4.6.3 Floating Terminals
        4. 9.4.6.4 TXD_INT Dominant Timeout (DTO)
        5. 9.4.6.5 CAN Bus Short Circuit Current Limiting
        6. 9.4.6.6 Thermal Shutdown
        7. 9.4.6.7 Under Voltage Lockout (UVLO) and Unpowered Device
          1. 9.4.6.7.1 UVSUP and UVCCOUT
          2. 9.4.6.7.2 UVIO
          3. 9.4.6.7.3 Fault and M_CAN Core Behavior:
      7. 9.4.7 CAN FD
    5. 9.5 Programming
      1. 9.5.1 SPI Communication
        1. 9.5.1.1 Chip Select Not (nCS):
        2. 9.5.1.2 SPI Clock Input (SCLK):
        3. 9.5.1.3 SPI Data Input (SDI):
        4. 9.5.1.4 SPI Data Output (SDO):
      2. 9.5.2 Register Descriptions
    6. 9.6 Register Maps
      1. 9.6.1 Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F
        1. 9.6.1.1 DEVICE_ID1[31:0] (address = h0000) [reset = h4E414354]
          1. Table 10. Device ID Field Descriptions
        2. 9.6.1.2 DEVICE_ID2[31:0] (address = h0004) [reset = h30353534]
          1. Table 11. Device ID Field Descriptions
        3. 9.6.1.3 Revision (address = h0008) [reset = h00110201]
          1. Table 12. Revision Field Descriptions
        4. 9.6.1.4 Status (address = h000C) [reset = h0000000U]
          1. Table 13. Status Field Descriptions
      2. 9.6.2 Device Configuration Registers: 16'h0800 to 16'h08FF
        1. 9.6.2.1 Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000468]
          1. Table 15. Modes of Operation and Pin Configuration Registers Field Descriptions
        2. 9.6.2.2 Timestamp Prescalar (address = h0804) [reset = h00000002]
          1. Table 16. EMC Enhancement and Timestamp Prescalar Field Descriptions
        3. 9.6.2.3 Test Register and Scratch Pad (address = h0808) [reset = h00000000]
          1. Table 17. Test and Scratch Pad Register Field Descriptions
        4. 9.6.2.4 Test Register (address = h080C) [reset = h00000000]
          1. Table 18. Test Register Field Descriptions
      3. 9.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830
        1. 9.6.3.1 Interrupts (address = h0820) [reset = h00100000]
          1. Table 19. Interrupts Field Descriptions
        2. 9.6.3.2 MCAN Interrupts (address = h0824) [reset = h00000000]
          1. Table 20. MCAN Interrupts Field Descriptions
        3. 9.6.3.3 Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]
          1. Table 21. Interrupt Enables Field Descriptions
      4. 9.6.4 CAN FD Register Set: 16'h1000 to 16'h10FF
        1. 9.6.4.1  Core Release Register (address = h1000) [reset = hrrrddddd]
          1. Table 25. Core Release Register Field Descriptions
        2. 9.6.4.2  Endian Register (address = h1004) [reset = h87654321]
          1. Table 26. Endian Register Field Descriptions
        3. 9.6.4.3  Customer Register (address = h1008) [reset = h00000000]
          1. Table 27. Customer Register Field Descriptions
        4. 9.6.4.4  Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]
          1. Table 28. Data Bit Timing & Prescaler Field Descriptions
        5. 9.6.4.5  Test Register (address = h1010 ) [reset = h00000000]
          1. Table 29. Test Register Field Descriptions
        6. 9.6.4.6  RAM Watchdog (address = h1014) [reset = h00000000]
          1. Table 30. RAM Watchdog Field Descriptions
        7. 9.6.4.7  Control Register (address = h1018) [reset = 0000 0019]
          1. Table 31. Control Register Field Descriptions
        8. 9.6.4.8  Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]
          1. Table 32. Nominal Bit Timing & Prescaler Register Field Descriptions
        9. 9.6.4.9  Timestamp Counter Configuration (address = h1020) [reset = h00000000]
          1. Table 33. Timestamp Counter Configuration Descriptions
        10. 9.6.4.10 Timestamp Counter Value (address = h1024) [reset = h00000000]
          1. Table 34. Timestamp Counter Value Field Descriptions
        11. 9.6.4.11 Timeout Counter Configuration (address = h1028) [reset = hFFFF0000]
          1. Table 35. Timeout Counter Configuration Field Descriptions
        12. 9.6.4.12 Timeout Counter Value (address = h102C) [reset = h0000FFFF]
          1. Table 36. Timeout Counter Value Field Descriptions
        13. 9.6.4.13 Reserved (address = h1030 - h103C) [reset = h00000000]
          1. Table 37. Reserved Field Descriptions
        14. 9.6.4.14 Error Counter Register (address = h1040) [reset = h00000000]
          1. Table 38. Error Counter Register Field Descriptions
        15. 9.6.4.15 Protocol Status Register (address = h1044) [reset = h00000707]
          1. Table 39. Protocol Status Register Field Descriptions
        16. 9.6.4.16 Transmitter Delay Compensation Register (address = h1048) [reset = h00000000]
          1. Table 40. Transmitter Delay Compensation Register Field Descriptions
        17. 9.6.4.17 Reserved (address = h104C) [reset = h00000000]
          1. Table 41. Reserved Field Descriptions
        18. 9.6.4.18 Interrupt Register (address = h1050) [reset = h00000000]
          1. Table 42. Interrupt Register Field Descriptions
        19. 9.6.4.19 Interrupt Enable (address = h1054) [reset = h00000000]
          1. Table 43. Interrupt Enable Field Descriptions
        20. 9.6.4.20 Interrupt Line Select (address = h1058) [reset = h00000000]
          1. Table 44. Interrupt Line Select Field Descriptions
        21. 9.6.4.21 Interrupt Line Enable (address = h105C) [reset = h00000000]
          1. Table 45. Interrupt Line Enable Field Descriptions
        22. 9.6.4.22 Reserved (address = h1060 - h107C) [reset = h00000000]
          1. Table 46. Reserved Field Descriptions
        23. 9.6.4.23 Global Filter Configuration (address = h1080) [reset = h00000000]
          1. Table 47. Global Filter Configuration Field Descriptions
        24. 9.6.4.24 Standard ID Filter Configuration (address = h1084) [reset = h00000000]
          1. Table 48. Standard ID Filter Configuration Field Descriptions
        25. 9.6.4.25 Extended ID Filter Configuration (address = h1088) [reset = h00000000]
          1. Table 49. Extended ID Filter Configuration Field Descriptions
        26. 9.6.4.26 Reserved (address = h108C) [reset = h00000000]
          1. Table 50. Reserved Field Descriptions
        27. 9.6.4.27 Extended ID AND Mask (address = h1090) [reset = h1FFFFFFF]
          1. Table 51. Extended ID AND Mask Field Descriptions
        28. 9.6.4.28 High Priority Message Status (address = h1094) [reset = h00000000]
          1. Table 52. High Priority Message Status Field Descriptions
        29. 9.6.4.29 New Data 1 (address = h1098) [reset = h00000000]
          1. Table 53. New Data 1 Field Descriptions
        30. 9.6.4.30 New Data 2 (address = h109C) [reset = h00000000]
          1. Table 54. New Data 2 Field Descriptions
        31. 9.6.4.31 Rx FIFO 0 Configuration (address = h10A0) [reset = h00000000]
          1. Table 55. Rx FIFO 0 Configuration Field Descriptions
        32. 9.6.4.32 Rx FIFO 0 Status (address = h10A4) [reset = h00000000]
          1. Table 56. Rx FIFO 0 Status Field Descriptions
        33. 9.6.4.33 Rx FIFO 0 Acknowledge (address = h10A8) [reset = h00000000]
          1. Table 57. Rx FIFO 0 Acknowledge Field Descriptions
        34. 9.6.4.34 Rx Buffer Configuration (address = h10AC) [reset = h00000000]
          1. Table 58. Rx Buffer Configuration Field Descriptions
        35. 9.6.4.35 Rx FIFO 1 Configuration (address = h10B0) [reset = h00000000]
          1. Table 59. Rx FIFO 1 Configuration Field Descriptions
        36. 9.6.4.36 Rx FIFO 1 Status (address = h10B4) [reset = h00000000]
          1. Table 60. Rx FIFO 1 Status Field Descriptions
        37. 9.6.4.37 Rx FIFO 1 Acknowledge (address = h10B8) [reset = h00000000]
          1. Table 61. Rx FIFO 1 Acknowledge Field Descriptions
        38. 9.6.4.38 Rx Buffer/FIFO Element Size Configuration (address = h10BC) [reset = h00000000]
          1. Table 62. Rx Buffer/FIFO Element Size Configuration Field Descriptions
        39. 9.6.4.39 Tx Buffer Configuration (address = h10C0) [reset = h00000000]
          1. Table 63. Tx Buffer Configuration Field Descriptions
        40. 9.6.4.40 Tx FIFO/Queue Status (address = h10C4) [reset = h00000000]
          1. Table 64. Tx FIFO/Queue Status Field Descriptions
        41. 9.6.4.41 Tx Buffer Element Size Configuration (address = h10C8) [reset = h00000000]
          1. Table 65. Tx Buffer Element Size Configuration Field Descriptions
        42. 9.6.4.42 Tx Buffer Request Pending (address = h10CC) [reset = h00000000]
          1. Table 66. Tx Buffer Request Pending Field Descriptions
        43. 9.6.4.43 Tx Buffer Add Request (address = h10D0) [reset = h00000000]
          1. Table 67.   Tx Buffer Add Request Field Descriptions
          2. 9.6.4.43.1  Tx Buffer Cancellation Request (address = h10D4 [reset = h00000000]
            1. Table 68. Tx Buffer Cancellation Request Field Descriptions
          3. 9.6.4.43.2  Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]
            1. Table 69. Tx Buffer Add Request Transmission Occurred Field Descriptions
          4. 9.6.4.43.3  Tx Buffer Cancellation Finished (address = h10DC) [reset = h00000000]
            1. Table 70. Tx Buffer Cancellation Finished Field Descriptions
          5. 9.6.4.43.4  Tx Buffer Transmission Interrupt Enable (address = h10E0) [reset = h00000000]
            1. Table 71. Tx Buffer Transmission Interrupt Enable Field Descriptions
          6. 9.6.4.43.5  Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]
            1. Table 72. Tx Buffer Cancellation Finished Interrupt Enable Field Descriptions
          7. 9.6.4.43.6  Reserved (address = h10E8) [reset = h00000000]
            1. Table 73. Reserved Field Descriptions
          8. 9.6.4.43.7  Reserved (address = h10EC) [reset = h00000000]
            1. Table 74. Reserved Field Descriptions
          9. 9.6.4.43.8  Tx Event FIFO Configuration (address = h10F0) [reset = h00000000]
            1. Table 75. Tx Event FIFO Configuration Field Descriptions
          10. 9.6.4.43.9  Tx Event FIFO Status (address = h10F4) [reset = h00000000]
            1. Table 76. Tx Event FIFO Status Field Descriptions
          11. 9.6.4.43.10 Tx Event FIFO Acknowledge (address = h10F8) [reset = h00000000]
            1. Table 77. Tx Event FIFO Acknowledge Field Descriptions
          12. 9.6.4.43.11 Reserved (address = h10FC) [reset = h00000000]
            1. Table 78. Reserved Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Design Consideration
      1. 10.1.1 Crystal and Clock Input Requirements
      2. 10.1.2 Bus Loading, Length and Number of Nodes
      3. 10.1.3 CAN Termination
        1. 10.1.3.1 Termination
        2. 10.1.3.2 CAN Bus Biasing
      4. 10.1.4 INH Brownout Behavior
    2. 10.2 Typical Application
      1. 10.2.1 Detailed Requirements
      2. 10.2.2 Detailed Design Procedures
      3. 10.2.3 Application Curves
      4. 10.2.4 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
        1. 13.1.1.1 CAN トランシーバの物理層の標準
        2. 13.1.1.2 EMC要件
        3. 13.1.1.3 準拠テストの要件
        4. 13.1.1.4 サポート・ドキュメント
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.6.4.15 Protocol Status Register (address = h1044) [reset = h00000707]

Figure 62. Protocol Status Register
31 30 29 28 27 26 25 24
RSVD
R
23 22 21 20 19 18 17 16
RSVD TDCV[6:0]
R R
15 14 13 12 11 10 9 8
RSVD PXE RFDF RBRS RESI DLEC[2:0]
R X X X X S
7 6 5 4 3 2 1 0
BO EW EP ACT[1:0] LEC[2:0]
R R R R S

Table 39. Protocol Status Register Field Descriptions

Bit Field Type Reset Description
31:24 RSVD R 0x0 Reserved
23 RSVD R 0x0 Reserved
22:16 TDCV[6:0] R 0x0 Transmitter Delay Compensation Value
0x00-0x7F – Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.
15 RSVD R 0 Reserved
14 PXE X 0 Protocol Exception Event
0 – No protocol exception event occurred since last read access
1 – Protocol exception event occurred
13 RFDF X 0 Received a CAN FD Message
This bit is set independent of acceptance filtering
0 – Since this bit was reset by the CPU, no CAN FD message has been received
1 – Message in CAN FD format with FDF flag set has been received
12 RBRS X 0 BRS flag of last received CAN FD Message
This bit is set together with RFDF, independent of acceptance filtering.
0 – Last received CAN FD message did not have its BRS flag set
1 – Last received CAN FD message had its BRS flag set
11 RESI X 0 ESI flag of last received CAN FD Message
This bit is set together with RFDF, independent of acceptance filtering.
0 – Last received CAN FD message did not have its ESI flag set
1 – Last received CAN FD message had its ESI flag set
10:8 DLEC[2:0] X 0x7 Data Phase Last Error Code
Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.
7 BO R 0 Bus_Off Status
0 – The M_CAN is not Bus_Off
1 – The M_CAN is in Bus_Off state
6 EW R 0 Warning Status
0 – Both error counters are below the Error_Warning limit of 96
1 – At least one of error counter has reached the Error_Warning limit of 96
5 EP R 0 Error Passive
0 – The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected
1 – The M_CAN is in the Error_Passive state
4:3 ACT[1:0] R 0x0 Activity
Monitors the module’s CAN communication state.
00 – Synchronizing - node is synchronizing on CAN communication
01 – Idle - node is neither receiver nor transmitter
10 – Receiver - node is operating as receiver
11 – Transmitter - node is operating as transmitter
2:0 LEC[2:0] S 0x7 Last Error Code
The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’ when a message has been transferred (reception or transmission) without error.
0 – No Error: No error occurred since LEC has been reset by successful reception or transmission
1 – Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
2 – Form Error: A fixed format part of a received frame has the wrong format.
3 – AckError: The message transmitted by the M_CAN was not acknowledged by another node.
4 – Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value was dominant.
5 – Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
6 – CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
7 – NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register.

NOTE

When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error

NOTE

The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily checkup whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences.