JAJSIF7J February 2019 – August 2021 TDA4VM , TDA4VM-Q1
PRODUCTION DATA
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The interfaces or signals described in Table 7-2through Table 7-10 correspond to the interfaces or signals available in multiplexing mode 0 (Primary Function).
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC electrical characteristics are specified for the different multiplexing modes (Functions).
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
BALL NAMES in Mode 0: WKUP_I2C0_SDA, WKUP_I2C0_SCL, MCU_I2C0_SDA, MCU_I2C0_SCL, I2C0_SDA, I2C0_SCL, I2C1_SDA, I2C1_SCL, EXTINTN | ||||||
BALL NUMBERS:H24 / J25 / H25 / J26 / AA5 / AC5 / AA6 / Y6 / AC18 H24/ J25 / H25 / J26 / AA5 / AC5 / AA6 / Y6 / AC18 | ||||||
1.8-V MODE | ||||||
VIL | Input low-level threshold | 0.3 × VDDSHV(1) | V | |||
VILSS | Input low-level threshold steady state | 0.3 × VDDSHV(1) | V | |||
VIH | Input high-level threshold | 0.7 × VDDSHV(1) | V | |||
VIHSS | Input high-level threshold steady state | 0.7 × VDDSHV(1) | V | |||
VHYS | Input Hysteresis Voltage | 0.1 × VDDSHV(1) | mV | |||
IIN | Input Leakage Current | VI = 1.8 V or 0 V | ±10 | µA | ||
VOL | Output low-level voltage | 0.2 × VDDSHV(1) | V | |||
IOL | Low Level Output Current | VOL(MAX) | 6 | mA | ||
3.3-V MODE | ||||||
VIL | Input low-level threshold | 0.3 × VDDSHV(1) | V | |||
VILSS | Input low-level threshold steady state | 0.25 × VDDSHV(1) | V | |||
VIH | Input high-level threshold | 0.7 × VDDSHV(1) | V | |||
VIHSS | Input high-level threshold steady state | 0.7 × VDDSHV(1) | V | |||
VHYS | Input Hysteresis Voltage | 0.05 × VDDSHV(1) | mV | |||
IIN | Input Leakage Current | VI = 3.3 V or 0 V | ±10 | µA | ||
VOL | Output low-level voltage | 0.4 × VDDSHV(1) | V | |||
IOL | Low Level Output Current | VOL(MAX) | 6 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
BALL NAMES in Mode 0: MCU_PORz, PORz | ||||||
BALL NUMBERS:H23 / J24 | ||||||
VIL | Input low-level threshold | 0.3 × VDDSHV(1) | V | |||
VILSS | Input low-level threshold steady state | 0.3 × VDDSHV(1) | V | |||
VIH | Input high-level threshold | 0.7 × VDDSHV(1) | V | |||
VIHSS | Input high-level threshold steady state | 0.7 × VDDSHV(1) | V | |||
VHYS | Input Hysteresis Voltage | 200 | mV | |||
IIN | Input Leakage Current | VI = 1.8 V or 0 V | ±10 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
HIGH FREQUENCY OSCILLATOR | ||||||
BALL NAMES: WKUP_OSC0_XO, WKUP_OSC0_XI, OSC1_XO, OSC1_XI | ||||||
BALL NUMBERS:M27 / M29 / P27 / P29 | ||||||
VIH | Input high-level threshold | 0.65 × VDDSHV(1) | V | |||
VIL | Input low-level threshold | 0.35 × VDDSHV(1) | V | |||
VHYS | Input Hysteresis Voltage | 49 | mV | |||
LOW FREQUENCY OSCILLATOR | ||||||
BALL NAMES: WKUP_LFOSC0_XO, WKUP_LFOSC0_XI | ||||||
BALL NUMBERS:N26 / N28 | ||||||
VIH | Input high-level threshold | 0.65 × VDDA_WKUP(1) | V | |||
VIL | Input low-level threshold | 0.35 × VDDA_WKUP(1) | V | |||
VHYS | Input Hysteresis Voltage | Active Mode | 85 | mV | ||
Bypass Mode | 324 | mV |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
BALL NAMES in Mode 0: MMC0_DAT[7:0], MMC0_CALPAD, MMC0_CMD, MMC0_DS, MMC0_CLK | ||||||
BALL NUMBERS:AG2 / AH1 / AG3 / AF4 / AE5 / AF3 / AG1 / AF2 / AE1 / AE3 / AE4 / AF1 | ||||||
VIL | Input low-level threshold | 0.35 × VDDSHV(1) | V | |||
VILSS | Input low-level threshold steady state | 0.20 | V | |||
VIH | Input high-level threshold | 0.65 × VDDSHV(1) | V | |||
VIHSS | Input high-level threshold steady state | 1.4 | V | |||
IIN | Input Leakage Current | VI = 1.8 V or 0 V | ±10 | µA | ||
IOZ | Tri-state Output Leakage Current | VO = 1.8 V or 0 V | ±10 | µA | ||
RPU | Pull-up Resistor | 15 | 20 | 25 | kΩ | |
RPD | Pull-down Resistor | 15 | 20 | 25 | kΩ | |
VOL | Output low-level voltage | 0.30 | V | |||
VOH | Output high-level voltage | VDDSHV - 0.30(1) | V | |||
IOL | Low Level Output Current | VOL(MAX) | 2 | mA | ||
IOH | High Level Output Current | VOH(MAX) | 2 | mA | ||
SRI | Input Slew Rate | 5E + 8 | V/s |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
BALL NAMES in Mode 0: MMC1_CLK, MMC1_CMD, MMC1_DAT[3:0], MMC2_CLK, MMC2_CMD, MMC2_DAT[3:0] | ||||||
BALL NUMBERS:P25 / R29 / R24 / P24 / R25 / R26 / T26 / T25 / T24 / T27 / T29 / T28 | ||||||
1.8-V MODE | ||||||
VIL | Input low-level threshold | 0.58 | V | |||
VILSS | Input low-level threshold steady state | 0.58 | V | |||
VIH | Input high-level threshold | 1.27 | V | |||
VIHSS | Input high-level threshold steady state | 1.7 | V | |||
VHYS | Input Hysteresis Voltage | 150 | mV | |||
IIN | Input Leakage Current | VI = 1.8 V or 0 V | ±10 | µA | ||
RPU | Pull-up Resistor | 40 | 50 | 60 | kΩ | |
RPD | Pull-down Resistor | 40 | 50 | 60 | kΩ | |
VOL | Output low-level voltage | 0.45 | V | |||
VOH | Output high-level voltage | VDDSHV- 0.45(1) | V | |||
IOL | Low Level Output Current | VOL(MAX) | 4 | mA | ||
IOH | High Level Output Current | VOH(MAX) | 4 | mA | ||
3.3-V Mode | ||||||
VIL | Input low-level threshold | 0.25 × VDDSHV(1) | V | |||
VILSS | Input low-level threshold steady state | 0.15 × VDDSHV(1) | V | |||
VIH | Input high-level threshold | 0.625 × VDDSHV(1) | V | |||
VIHSS | Input high-level threshold steady state | 0.625 × VDDSHV(1) | V | |||
VHYS | Input Hysteresis Voltage | 150 | mV | |||
IIN | Input Leakage Current | VI = 1.8 V or 0 V | ±10 | µA | ||
RPU | Pull-up Resistor | 40 | 50 | 60 | kΩ | |
RPD | Pull-down Resistor | 40 | 50 | 60 | kΩ | |
VOL | Output low-level voltage | 0.125 × VDDSHV(1) | V | |||
VOH | Output high-level voltage | 0.75 × VDDSHV(1) | V | |||
IOL | Low Level Output Current | VOL(MAX) | 6 | mA | ||
IOH | High Level Output Current | VOH(MAX) | 10 | mA |
The CSI2/DSI DPHY interfaces electrical characteristics are compliant with the MIPI D-PHY Specifications v1.2 (August 1, 2014).
PARAMETER | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|
BALL NAMES in Mode 0: CSI0_RXCLKN, CSI0_RXCLKP, CSI0_RXRCALIB, CSI0_RXN[3:0], CSI0_RXP[3:0], CSI1_RXCLKN, CSI1_RXCLKP, CSI1_RXRCALIB, CSI1_RXN[3:0], CSI1_RXP[3:0], DSI_TXCLKN, DSI_TXCLKP, DSI_TXN[3:0], DSI_TXP [3:0], DSI_TXRCALIB | |||||
BALL NUMBERS: A14 / A15 / A17 / A18 / A20 / A21 / B13 / B14 / B16 / B17 / B19 / B20 / C12 / C13 / C15 / C16 / C18 / C19 / D11 / D12 / D14 / D15 / D17 / D18 / E10 / E11 / E13 / E14 / E16 / E17 / F12 / F15 / F16 | |||||
Low-Power Receiver (LP-RX) | |||||
VIH | Input high-level threshold | 740 | mV | ||
VIL | Input low-level threshold | 550 | mV | ||
VHYS | Hysteresis | 25 | mV | ||
Ultra-Low Power Receiver (ULP-RX) | |||||
VITH | Input high-level threshold | 740 | mV | ||
VITL-ULPM | Input low-level threshold | 300 | mV | ||
VHYS | Hysteresis | 25 | mV | ||
High Speed Receiver (HS-RX) | |||||
VIDTH | Differential input high-level threshold | 40 | mV | ||
VIDTL | Differential input low-level threshold | -40 | mV | ||
VIDMAX | Maximum differential input voltage | 270 | mV | ||
VILHS | Single-ended input low-level threshold | -40 | mV | ||
VIHHS | Single-ended input high-level threshold | 460 | mV | ||
VCMRXDC | Common-mode voltage | 70 | 330 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
BALL NAMES in Mode 0: MCU_ADC0_AIN[7:0], MCU_ADC1_AIN[7:0] | ||||||
BALL NUMBERS:K24 / K25 / K26 / K27 / K28 / K29 / L24 / L25 / L26 / L27 / L28 / L29 / M24 / M25 / N23 / N24 | ||||||
Analog Input | ||||||
VMCU_ADC0/1_AIN[7:0] | Full-scale Input Range | VSS | VDDA_ADC0/1 | V | ||
DNL | Differential Non-Linearity | -1 | 0.5 | 4 | LSB | |
INL | Integral Non-Linearity | ±1 | ±4 | LSB | ||
LSBGAIN-ERROR | Gain Error | ±2 | LSB | |||
LSBOFFSET-ERROR | Offset Error | ±2 | LSB | |||
CIN | Input Sampling Capacitance | 5.5 | pF | |||
SNR | Signal-to-Noise Ratio | Input Signal: 200 kHz sine wave at -0.5 dB Full Scale | 70 | dB | ||
THD | Total Harmonic Distortion | Input Signal: 200 kHz sine wave at -0.5 dB Full Scale | 73 | dB | ||
SFDR | Spurious Free Dynamic Range | Input Signal: 200 kHz sine wave at -0.5 dB Full Scale | 76 | dB | ||
SNR(PLUS) | Signal-to-Noise Plus Distortion | Input Signal: 200 kHz sine wave at -0.5 dB Full Scale | 69 | dB | ||
RMCU_ADC0/1_AIN[0:7] | Input Impedance of MCU_ADC0/1_AIN[7:0] | f = input frequency | [1/((65.97 × 10–-12) × fSMPL_CLK)] | Ω | ||
IIN | Input Leakage | MCU_ADC0/1_AIN[7:0] = VSS | -10 | μA | ||
MCU_ADC0/1_AIN[7:0] = VDDA_ADC0/1 | 24 | μA | ||||
Sampling Dynamics | ||||||
FSMPL_CLK | SMPL_CLK Frequency | 60 | MHz | |||
tC | Conversion Time | 13 | ADC0/1 SMPL_CLK Cycles | |||
tACQ | Acquisition time | 2 | 257 | ADC0/1 SMPL_CLK Cycles | ||
TR | Sampling Rate | ADC0/1 SMPL_CLK = 60 MHz | 4 | MSPS | ||
CCISO | Channel to Channel Isolation | 100 | dB | |||
General Purpose Input Mode(1) | ||||||
VIL | Input low-level threshold | 0.35 × VDDA_ADC0/1 | V | |||
VILSS | Input high-level threshold steady state | 0.35 × VDDA_ADC0/1 | V | |||
VIH | Input high-level threshold | 0.65 × VDDA_ADC0/1 | V | |||
VIHSS | Input high-level threshold steady state | 0.65 × VDDA_ADC0/1 | V | |||
VHYS | Input Hysteresis Voltage | 200 | mV | |||
IIN | Input Leakage Current | VI = 1.8 V or 0 V | 6 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
BALL NAMES in Mode 0: MLB0_MLBSN, MLB0_MLBDP, MLB0_MLBSP, MLB0_MLBCP, MLB0_MLBDN, MLB0_MLBCN | ||||||||
BALL NUMBERS:AC1 / AC3 / AD1 / AD2 / AD3 / AE2 | ||||||||
VIL | Input Low Voltage | 0.3 × VDD(1) | V | |||||
VILSS | Input Low Voltage Steady State | 0.3 × VDD(1) | V | |||||
VIH | Input High Voltage | 0.7 × VDD(1) | V | |||||
VIHSS | Input High Voltage Steady State | 0.75 × VDD(1) | V | |||||
VHYS | Input Hysteresis Voltage | 80 | mV | |||||
IIN | Input Leakage Current | VI = 1.8 V or 0 V | ±10 | µA | ||||
RPD | Pull-down Resistor | 20 | 53 | 130 | kΩ | |||
VOL | Output Low Voltage | 0.2 | V | |||||
VOH | Output High Voltage | VDD - 0.2 | V | |||||
IOL | Low Level Output Current | VOL(MAX) | 6 | mA | ||||
IOH | High Level Output Current | VOH(MIN) | 6 | mA | ||||
SRI | Input Slew Rate(2) | fop > 100 MHz | 1 | V/ns | ||||
fop < 1 MHz | 10 | V/ns |
PARAMETER(1) | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
BALL NAMES: ALL other IOs | |||||||
BALL NUMBERS: ALL other IOs | |||||||
1.8-V MODE | |||||||
VIL | Input Low Voltage | 0.35 × VDD(1) | V | ||||
VILSS | Input Low Voltage Steady State | 0.3 × VDD(1) | V | ||||
VIH | Input High Voltage | 0.65 × VDD(1) | V | ||||
VIHSS | Input High Voltage Steady State | 0.85 × VDD(1) | V | ||||
VHYS | Input Hysteresis Voltage | 150 | mV | ||||
IIN | Input Leakage Current. | VI = 1.8 V or 0 V | ±10 | µA | |||
RPU | Pull-up Resistor | 15 | 22 | 30 | kΩ | ||
RPD | Pull-down Resistor | 15 | 22 | 30 | kΩ | ||
VOL | Output Low Voltage | 0.45 | V | ||||
VOH | Output High Voltage | VDD(1) - 0.45 | V | ||||
IOL | Low Level Output Current | VOL(MAX) | 3 | mA | |||
IOH | High Level Output Current | VOH(MIN) | 3 | mA | |||
3.3-V MODE | |||||||
VIL | Input Low Voltage | 0.8 | V | ||||
VILSS | Input Low Voltage Steady State | 0.6 | V | ||||
VIH | Input High Voltage | 2.0 | V | ||||
VIHSS | Input High Voltage Steady State | 2.0 | V | ||||
VHYS | Input Hysteresis Voltage | 150 | mV | ||||
IIN | Input Leakage Current. | VI = 3.3 V or 0 V | ±10 | µA | |||
RPD | Pull-down Resistor | 15 | 22 | 30 | kΩ | ||
VOL | Output Low Voltage | 0.4 | V | ||||
VOH | Output High Voltage | 2.4 | V | ||||
IOL | Low Level Output Current | VOL(MAX) | 5 | mA | |||
IOH | High Level Output Current | VOH(MIN) | 6 | mA |
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base Specification Revision 4.0, September 27, 2017.
This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal termination enabled, as described by parameter VREFCLK_TERM in Table 7-11, 4-L-PHY SERDES REFCLK Electrical Characteristics. Internal termination is enabled by default and must be disabled before applying a reference clock signal that exceeds the limits defined by VREFCLK_TERM. External termination should always be enabled on the source side.
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
BALL NAMES in Mode 0: SERDES4_REFCLK_P, SERDES4_REFCLK_N | |||||
BALL NUMBERS:E8 / E7 | |||||
VREFCLK_TERM | Single ended voltage threshold at the reference clock pin when internal termination is enabled | 400 | mV | ||
RTERM | Internal termination | 40 | 50 | 62.5 | Ω |
The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July 26, 2013.
The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3 Clause 70.
The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.
The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.
The UFS interface electrical characteristics are compliant with MIPI M-PHY Specification v3.1, February 17, 2014.
The DP interface electrical characteristics are compliant with the VESA DisplayPort (DP) Standard v 1.4 February 23, 2016.
The eDP interface electrical characteristics are compliant with the VESA Embedded DisplayPort (eDP) Standard v1.4b October 23, 2015.
The DDR interface is compatible with JESD209-4B standard compliant LPDDR4 SDRAM devices.