JAJSIK7 February   2020 THP210

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      高精度、低ノイズ、低消費電力の完全差動アンプのゲイン・ブロックとインターフェイス
      2.      小さな入力電圧オフセット
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Super-Beta Input Bipolar Transistors
      2. 7.3.2 Power Down
      3. 7.3.3 Flexible Gain Setting
      4. 7.3.4 Amplifier Overload Power Limit
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Driving Capacitive Loads
      2. 8.1.2 Operating the Power-Down Feature
      3. 8.1.3 Noise Performance
    2. 8.2 Typical Applications
      1. 8.2.1 An MFB Filter Driving an ADC Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

at TA = 25°C, VS = ±1.5 V to ±18 V, VOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2 kΩ, and RL = 10 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VIO Input-referred offset voltage 10 ±40 µV
TA = –40°C to 125°C ±80 µV
Input offset voltage drift TA = –40°C to 125°C 0.1 ±0.4 µV/°C
PSRR Power-supply rejection ratio 0.025 0.25 µV/V
TA = –40°C to 125°C 0.5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±0.2 ±2 nA
TA = –40°C to 125°C ±4 nA
Input bias current drift TA = –40°C to 125°C ±2 ±15 pA/°C
IOS Input offset current ±0.2 ±1 nA
TA = –40°C to 125°C ±3 nA
Input offset current drift TA = –40°C to 125°C 1 ±10 pA/°C
NOISE
en Input differential voltage noise f = 1 kHz 3.7 nV/√Hz
f = 10 Hz 4 nV/√Hz
f = 0.1 to 10 Hz 0.1 µVpp
ei Input current noise, each input f = 1 kHz 300 fA/√Hz
f = 10 Hz 400 fA/√Hz
f = 0.1 to 10 Hz 13.4 pApp
INPUT VOLTAGE
Common-mode voltage range TA = –40°C to 125°C VVS– + 1 VVS+ – 1 V
CMRR Common-mode rejection ratio VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V
140

dB
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V 126 140
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V, TA = –40°C to   +125°C 120
INPUT IMPEDANCE
Input impedance differential mode VICM = 0 V 1 || 1 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = ±2.5 V, VVS– + 0.2 V < VO < VVS+ – 0.2 V 115 120 dB
VS = ±2.5 V, VVS– + 0.3 V < VO < VVS+ – 0.3 V, TA = –40°C to +125°C 115 120 dB
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V 115 120 dB
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V, TA = –40°C to +125°C 110 120 dB
FREQUENCY RESPONSE
SSBW Small-signal bandwidth VO = 100 mVPP, G = –1 V/V 7 MHz
GBP Gain-bandwidth product VO = 100 mVPP, G = –10 V/V 9.2 MHz
FBP Full-power bandwidth VO = –1 VPP, G = –1 V/V 2.4 MHz
SR Slew rate G = –1, 10-V step 15 V/µs
Settling time To 0.1% of final value, G = –1 V/V, VO = 10-V step 1 µs
To 0.01% of final value, G = –1 V/V, VO= 10-V step 2 µs
THD+N Total harmonic distortion and Noise Differential input, f = 10 kHz, VO = 10 VPP –120 dB
Total harmonic distortion and Noise Single-ended input, f = 10 kHz, VO = 10 VPP –115 dB
HD2 Second-order harmonic distortion Differential input, f = 10 kHz, VO = 10 VPP –120 dB
Single-ended input, f = 10 kHz, VO = 10 VPP –120 dB
HD3 Third-order harmonic distortion Differential input, f = 10 kHz, VO = 10 VPP –120 dB
Single-ended input, f = 10 kHz, VO = 10 VPP –120 dB
Overdrive recovery time G = 5 V/V, 2x output overdrive, dc-coupled 3.3 µs
ZO Open-loop output impedance f = 100 kHz (differential) 14 Ω
CLOAD Capacitive load drive Differential capacitive load, no output isolation resistors, phase margin = 30° 50 pF
OUTPUT
VOL, VOH Output voltage range low, high VS = ±2.5 V 100 mV
VS = ±2.5 V, TA = –40°C to 125°C 100 mV
VS = ±18 V 230 mV
VS = ±18 V, TA = –40°C to 125°C 270 mV
ISC Short-circuit current ±31 mA
OUTPUT COMMON-MODE VOLTAGE
Small-signal bandwidth from VOCM pin VVOCM = 100 mVPP 2 MHz
Large-signal bandwidth from VOCM pin VVOCM = 0.6 VPP 5.7 MHz
Slew rate from VOCM pin VVOCM = 0.5-V step, rising 3.5 V/µs
VVOCM = 0.5-V step, falling 5.5 V/µs
DC output balance VVOCM fixed midsupply (VO = ±1 V) 78 dB
Output balance SSBW VVOCM fixed midsupply, V/ VOCM (–3 dB from dc) TBD kHz
Output balance LSBW VVOCM fixed midsupply, V/ VOCM with
VO = 5 VPP (–3 dB from dc)
TBD kHz
VOCM Input Voltage Range VS = ±2.5 V VVS– + 1 VVS+ – 1
VS = ±18 V VVS– + 2 VVS+ – 2
VOCM input impedance 2.5  || 1 MΩ || pF
VOCM offset from mid-supply VVOCMpin floating, VO = VICM = 0 V ±1 mV
VOCM common-mode offset voltage VVOCM = VICM, VO = 0 V ±1 ±6 mV
VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C ±10 mV
VOCMcommon-mode offset voltage drift VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C ±20 ±60 µV/°C
POWER SUPPLY
IQ Quiescent operating current 0.95 1.1 mA
TA = –40°C to +125°C 1.5 mA
POWER DOWN
VPD(HI) Power-down enable voltage TA = –40°C to +125°C VVS+ – 0.5 V
VPD(LOW) Power-down disable voltage TA = –40°C to +125°C VVS+ – 2.0 V
PD bias current VPD = VVS+ – 2 V 1 2 µA
Powerdown quiescent current 10 20 µA
Turn-on time delay Time to VO = 90% of final value 10 µs
Turn-off time delay Time to VO = 10% of original value 15 µs