JAJSIK7 February   2020 THP210

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      高精度、低ノイズ、低消費電力の完全差動アンプのゲイン・ブロックとインターフェイス
      2.      小さな入力電圧オフセット
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Super-Beta Input Bipolar Transistors
      2. 7.3.2 Power Down
      3. 7.3.3 Flexible Gain Setting
      4. 7.3.4 Amplifier Overload Power Limit
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Driving Capacitive Loads
      2. 8.1.2 Operating the Power-Down Feature
      3. 8.1.3 Noise Performance
    2. 8.2 Typical Applications
      1. 8.2.1 An MFB Filter Driving an ADC Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Operating the Power-Down Feature

The power-down feature on the THP210 allows the device to be put into a low power-consumption state, in which quiescent current is minimized. To force the device into the low-power state, drive the PD pin to less than 2 V less than the positive supply voltage (VVS+ – 2 V). Driving the PD pin to less than 2 V forces the internal logic to disable both the differential and common-mode amplifiers. The PD pin has an internal pullup current that allows for the pin to be used in an open-drain MOSFET configuration without an additional pullup resistor, as seen in Figure 12. In this configuration, the logic level can be referenced to the MOSFET, and the voltage at the PD pin is level-shifted to account for use with high supply voltages. Be sure to select an N-type MOSFET with a maximum BVDSS greater than the total supply voltage.

THP210 thp210-pin-functionality.gifFigure 12. Power-Down (PD) Pin Interface With Low-Voltage Logic Level Signals

For applications that do not use the power-down feature, tie the PD pin to the positive supply voltage.

When PD is low (device is in power down) the output pins will be in a high-impedance state.