JAJSEM1F March   2001  – August 2016 TLV2370 , TLV2371 , TLV2372 , TLV2373 , TLV2374 , TLV2375

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     オペアンプ
  4. 4 改訂履歴
  5. 5 Device Comparison Tables
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: TLV2370
    2.     Pin Functions: TLV2371
    3.     Pin Functions: TLV2372
    4.     Pin Functions: TLV2373
    5.     Pin Functions: TLV2374
    6.     Pin Functions: TLV2375
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Thermal Information: TLV2370
    4. 7.4 Thermal Information: TLV2371
    5. 7.5 Thermal Information: TLV2372
    6. 7.6 Thermal Information: TLV2373
    7. 7.7 Thermal Information: TLV2374
    8. 7.8 Thermal Information: TLV2375
    9. 7.9 Electrical Characteristics
  8. 8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Rail-to-Rail Input Operation
      2. 9.3.2 Driving a Capacitive Load
      3. 9.3.3 Offset Voltage
      4. 9.3.4 General Configurations
      5. 9.3.5 Shutdown Function
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Power Dissipation Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.9 Electrical Characteristics

at TA = 25°C, VDD = 2.7 V, 5 V, and 15 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC PERFORMANCE
VOS Input offset voltage At TA = 25°C, VIC = VDD/2, VO = VDD/2, RS = 50 Ω 2 4.5 mV
At TA = –40°C to +125°C, VIC = VDD/2, VO = VDD/2,
RS = 50 Ω		 6 mV
dVOS/dT Offset voltage drift At TA = 25°C, VIC = VDD/2, VO = VDD/2, RS = 50 Ω 2 µV/°C
CMRR Common-mode rejection ratio VDD = 2.7 V,
RS = 50 Ω		 VIC = 0 to VDD 50 68 dB
At TA = –40°C to +125°C,
VIC = 0 to VDD 		49
VIC = 0 to VDD − 1.35 V 56 70
At TA = –40°C to +125°C,
VIC = 0 to VDD − 1.35 V		 54
VDD = 5 V,
RS = 50 Ω		 VIC = 0 to VDD 55 72
At TA = –40°C to +125°C,
VIC = 0 to VDD 		54
VIC = 0 to VDD − 1.35 V 67 80
At TA = –40°C to +125°C,
VIC = 0 to VDD − 1.35 V		 64
VDD = 15 V,
RS = 50 Ω		 VIC = 0 to VDD 64 82
At TA = –40°C to +125°C,
VIC = 0 to VDD 		63
VIC = 0 to VDD − 1.35 V 67 84
At TA = –40°C to +125°C,
VIC = 0 to VDD − 1.35 V		 66
AVD Large-signal differential voltage amplification VDD = 2.7 V,
VO(PP) = VDD/2,
RL = 10 kΩ		 98 106 dB
At TA = –40°C to +125°C 76
VDD = 5 V,
VO(PP) = VDD/2,
RL = 10 kΩ		 100 110
At TA = –40°C to +125°C 86
VDD = 15 V,
VO(PP) = VDD/2,
RL = 10 kΩ		 81 83
At TA = –40°C to +125°C 79
INPUT CHARACTERISTICS
IOS Input offset current VDD = 15 V,
VIC = VO = VDD/2		 1 60 pA
At TA = 70°C 100
At TA = 125°C 1000
IB Input bias current VDD = 15 V,
VIC = VO = VDD/2		 1 60 pA
At TA = 70°C 100
At TA = 125°C 1000
Differential input resistance 1000 GΩ
Common-mode input capacitance f = 21 kHz 8 pF
OUTPUT CHARACTERISTICS
VOH High-level output voltage VDD = 2.7 V At TA = 25°C, VIC = VDD/2, IOH = −1 mA 2.55 2.58 V
At TA = –40°C to +125°C, VIC = VDD/2,
IOH = −1 mA		 2.48
VDD = 5 V At TA = 25°C, VIC = VDD/2, IOH = −1 mA 4.9 4.93
At TA = –40°C to +125°C, VIC = VDD/2,
IOH = −1 mA		 4.85
VDD = 15 V At TA = 25°C, VIC = VDD/2, IOH = −1 mA 14.92 14.96
At TA = –40°C to +125°C, VIC = VDD/2,
IOH = −1 mA		 14.9
VDD = 2.7 V At TA = 25°C, VIC = VDD/2, IOH = −5 mA 1.9 2
At TA = –40°C to +125°C, VIC = VDD/2,
IOH = −5 mA		 1.6
VDD = 5 V At TA = 25°C, VIC = VDD/2, IOH = −5 mA 4.6 4.68
At TA = –40°C to +125°C, VIC = VDD/2,
IOH = −5 mA		 4.5
VDD = 15 V At TA = 25°C, VIC = VDD/2, IOH = −5 mA 14.7 14.8
At TA = –40°C to +125°C, VIC = VDD/2,
IOH = −5 mA		 14.6
VOL Low-level output voltage VDD = 2.7 V At TA = 25°C, VIC = VDD/2, IOL = 1 mA 0.1 0.15
At TA = –40°C to +125°C, VIC = VDD/2,
IOL = 1 mA		 0.22 V
VDD = 5 V At TA = 25°C, VIC = VDD/2, IOL = 1 mA 0.05 0.1
At TA = –40°C to +125°C, VIC = VDD/2,
IOL = 1 mA		 0.15
VDD = 15 V At TA = 25°C, VIC = VDD/2, IOL = 1 mA 0.05 0.08
At TA = –40°C to +125°C, VIC = VDD/2,
IOL = 1 mA		 0.1
VDD = 2.7 V At TA = 25°C, VIC = VDD/2, IOL = 5 mA 0.52 0.7
At TA = –40°C to +125°C, VIC = VDD/2,
IOL = 5 mA		 1.1
VDD = 5 V At TA = 25°C, VIC = VDD/2, IOL = 5 mA 0.28 0.4
At TA = –40°C to +125°C, VIC = VDD/2,
IOL = 5 mA		 0.5
VDD = 15 V At TA = 25°C, VIC = VDD/2, IOL = 5 mA 0.19 0.3
At TA = –40°C to +125°C, VIC = VDD/2,
IOL = 5 mA		 0.35
IO Output current VDD = 2.7 V,
VO = 0.5 V from rail		 Positive rail 4 mA
Negative rail 5
VDD = 5 V,
VO = 0.5 V from rail		 Positive rail 7
Negative rail 8
VDD = 15 V,
VO = 0.5 V from rail		 Positive rail 16
Negative rail 15
POWER SUPPLY
IDD Supply current (per channel) VDD = 2.7 V, VO = VDD/2 470 560 µA
VDD = 5 V, VO = VDD/2 550 660
VDD = 15 V,
VO = VDD/2		 At TA = 25°C 750 900
At TA = –40°C to +125°C 1200
PSRR Power-supply rejection ratio (ΔVDD/ΔVIO) VDD = 2.7 V to 15 V,
VIC = VDD/2, no load		 At TA = 25°C 70 80 dB
At TA = –40°C to +125°C 65
DYNAMIC PERFORMANCE
UGBW Unity gain bandwidth VDD = 2.7 V RL = 2 kΩ, CL = 10 pF 2.4 MHz
VDD = 5 V to 15 V RL = 2 kΩ, CL = 10 pF 3
SR Slew rate at unity gain VDD = 2.7 V At TA = 25°C, VO(PP) = VDD/2,
CL = 50 pF, RL = 10 kΩ		 1.4 2 V/µs
At TA = –40°C to +125°C, VO(PP) = VDD/2,
CL = 50 pF, RL = 10 kΩ		 1
VDD = 5 V At TA = 25°C, VO(PP) = VDD/2,
CL = 50 pF, RL = 10 kΩ		 1.6 2.4
At TA = –40°C to +125°C, VO(PP) = VDD/2,
CL = 50 pF, RL = 10 kΩ		 1.2
VDD = 15 V At TA = 25°C, VO(PP) = VDD/2,
CL = 50 pF, RL = 10 kΩ		 1.9 2.1
At TA = –40°C to +125°C, VO(PP) = VDD/2,
CL = 50 pF, RL = 10 kΩ		 1.4
φm Phase margin RL = 2 kΩ, CL = 100 pF 65 °
Gain margin RL = 2 kΩ, CL = 10 pF 18 dB
ts Settling time VDD = 2.7 V, V(STEP)PP = 1 V, AV = −1,
CL = 10 pF, RL = 2 kΩ, 0.1%		 2.9 µs
VDD = 5 V, 15 V, V(STEP)PP = 1 V, AV = −1,
CL = 47 pF, RL = 2 kΩ, 0.1%		 2
NOISE, DISTORTION PERFORMANCE
THD + N Total harmonic distortion plus noise VDD = 2.7 V VO(PP)= VDD/2 V, RL = 2 kΩ,
f = 10 kHz, AV = 1		 0.02%
VO(PP)= VDD/2 V, RL = 2 kΩ,
f = 10 kHz, AV = 10		 0.05%
VO(PP)= VDD/2 V, RL = 2 kΩ,
f = 10 kHz, AV = 100		 0.18%
VDD = 5 V,
15 V		 VO(PP)= VDD/2 V, RL = 2 kΩ,
f = 10 kHz, AV = 1		 0.02%
VO(PP)= VDD/2 V, RL = 2 kΩ,
f = 10 kHz, AV = 10		 0.09%
VO(PP)= VDD/2 V, RL = 2 kΩ,
f = 10 kHz, AV = 100		 0.5%
Vn Equivalent input noise voltage f = 1 kHz 39 nV/√Hz
f = 10 kHz 35
In Equivalent input noise current f = 1 kHz 0.6 fA/√Hz
SHUTDOWN CHARACTERISTICS
IDD(SHDN) Supply current in shutdown mode (TLV2370, TLV2373, TLV2375) (per channel) VDD = 2.7 V, 5 V,
SHDN = 0 V		 At TA = 25°C 25 30 µA
At TA = –40°C to +125°C 35
VDD = 15 V,
SHDN = 0 V		 At TA = 25°C 40 45
At TA = –40°C to +125°C 50
t(on) Amplifier turnon time(1) RL = 2 kΩ 0.8 µs
t(off) Amplifier turnoff time(1) RL = 2 kΩ 1 µs
(1) Disable time and enable time are defined as the interval between application of the logic signal to the SHDN terminal and the point at which the supply current has reached one half of its final value.