JAJSEU0G March   2003  – February 2018 TLV2460A-Q1 , TLV2461A-Q1 , TLV2462-Q1 , TLV2462A-Q1 , TLV2463A-Q1 , TLV2464A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information: TLV2460x-Q1
    5. 6.5  Thermal Information: TLV2461x-Q1
    6. 6.6  Thermal Information: TLV2462-Q1
    7. 6.7  Thermal Information: TLV2462A-Q1
    8. 6.8  Thermal Information: TLV2463x-Q1
    9. 6.9  Electrical Characteristics: VDD = 3 V
    10. 6.10 Electrical Characteristics: VDD = 5 V
    11. 6.11 Operating Characteristics: VDD = 3 V
    12. 6.12 Operating Characteristics: VDD = 5 V
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Driving a Capacitive Load
      2. 8.3.2 Offset Voltage
      3. 8.3.3 General Configurations
      4. 8.3.4 General Power Dissipation Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Function
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Macromodel Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • PW|8
サーマルパッド・メカニカル・データ
発注情報

6.9 Electrical Characteristics: VDD = 3 V

at specified free-air temperature, VDD = 3 V, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage VDD = 3 V
VIC = 1.5 V
VO = 1.5 V
RS = 50 Ω		 TLV246x-Q1 TA = 25°C 100 2000 μV
Full range(1) 2200
TLV246xA-Q1 TA = 25°C 150 1500
Full range(1) 1700
αVIO Temperature coefficient of input offset voltage VDD = 3 V
VIC = 1.5 V
VO = 1.5 V
RS = 50 Ω		 2 μV/°C
IIO Input offset current VDD = 3 V
VIC = 1.5 V
VO = 1.5 V
RS = 50 Ω		 TA = 25°C 2.8 7 nA
Full range(1) 75
IIB Input bias current VIC = 1.5 V
VO = 1.5 V
RS = 50 Ω		 TA = 25°C 4.4 14 nA
Full range(1) 75
VOH High-level output voltage IO = –2.5 mA TA = 25°C 2.9 V
Full range(1) 2.8
IO = –10 mA TA = 25°C 2.7
Full range(1) 2.5
VOL Low-level output voltage VIC = 1.5 V
IOL = 2.5 mA		 TA = 25°C 0.1 V
Full range(1) 0.2
VIC = 1.5 V
IOL = 10 mA		 TA = 25°C 0.3
Full range(1) 0.5
IOS Short circuit output current Sourcing TA = 25°C 50 mA
Full range(1) 20
Sinking TA = 25°C 40
Full range 20
IO Output current Measured 1 V from rail TA = 25°C ±40 mA
AVD Large-signal differential voltage amplification RL = 10 kΩ TA = 25°C 90 105 dB
Full range(1) 89
ri(d) Differential input resistance TA = 25°C 109 Ω
ci(o) Common-mode input capacitance f = 10 kHz TA = 25°C 7 pF
zo Closed-loop output impedance f = 100 kHz
AV = 10		 TA = 25°C 33 Ω
CMRR Common-mode rejection ratio VICR = 0 V to 3 V
RS = 50 Ω		 TA = 25°C 66 80 dB
Full range(1) 60
kSVR Supply-voltage rejection ratio (ΔVDD± / ΔVIO) VDD = 2.7 V to 6 V
VIC = VDD / 2; no load		 TA = 25°C 80 85 dB
Full range(1) 75
VDD = 3 V to 5 V
VIC = VDD / 2; no load		 TA = 25°C 85 95
Full range(1) 80
IDD Supply current (per channel) VO = 1.5 V; no load TA = 25°C 0.5 0.575 mA
Full range(1) 0.9
IDD(SHDN) Supply current in shutdown (TLV2460-Q1,
TLV2463-Q1)		 SHDN < 0.7 V, per channel in shutdown TA = 25°C 0.3 μA
Full range(1) 2.5
(1) Full range is –40°C to +125°C.