JAJSGC5D February   2011  – December 2018 TMP103

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 One-Shot Mode
      3. 7.4.3 Continuous Conversion Mode
    5. 7.5 Programming
      1. 7.5.1  Temperature Watchdog Function
      2. 7.5.2  Conversion Rate
      3. 7.5.3  Shutdown Mode (M1 = 0, M0 = 0)
      4. 7.5.4  One-Shot (M1 = 0, M0 = 1)
      5. 7.5.5  Continuous Conversion Mode (M1 = 1)
      6. 7.5.6  Bus Overview
      7. 7.5.7  Serial Interface
      8. 7.5.8  Serial Bus Address
      9. 7.5.9  Writing and Reading Operation
      10. 7.5.10 Slave Mode Operations
        1. 7.5.10.1 Slave Receiver Mode
        2. 7.5.10.2 Slave Transmitter Mode
      11. 7.5.11 General Call
      12. 7.5.12 High-Speed (Hs) Mode
      13. 7.5.13 Timeout Function
      14. 7.5.14 Multiple Device Access
        1. 7.5.14.1 Multiple Device Access Write
        2. 7.5.14.2 Multiple Device Access Read
      15. 7.5.15 NOISE
    6. 7.6 Register Maps
      1. 7.6.1 Pointer Register
      2. 7.6.2 Temperature Register
      3. 7.6.3 Configuration Register
      4. 7.6.4 Temperature Limit Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • YFF|4
サーマルパッド・メカニカル・データ
発注情報

7.5.6 Bus Overview

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.

To address a specific device, a START condition is initiated, indicated by pulling the data line (SDA) from a high to low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge of the clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data transfer, SDA must remain stable while SCL is high, because any change in SDA while SCL is high is interpreted as a START or STOP signal.

Once all data have been transferred, the master generates a STOP condition indicated by pulling SDA from low to high, while SCL is high.