JAJSF26E March   2018  – August 2021 TMP1075

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics:TMP1075
    6. 8.6  Electrical Characteristics: TMP1075N
    7. 8.7  Timing Requirements:TMP1075
    8. 8.8  Timing Requirements: TMP1075N
    9. 8.9  Switching Characteristics
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital Temperature Output
      2. 9.3.2 I2C and SMBus Serial Interface
        1. 9.3.2.1  Bus Overview
        2. 9.3.2.2  Serial Bus Address
        3. 9.3.2.3  Pointer Register
          1. 9.3.2.3.1 Pointer Register Byte [reset = 00h]
        4. 9.3.2.4  Writing and Reading to the TMP1075
        5. 9.3.2.5  Operation Mode
          1. 9.3.2.5.1 Receiver Mode
          2. 9.3.2.5.2 Transmitter Mode
        6. 9.3.2.6  SMBus Alert Function
        7. 9.3.2.7  General Call- Reset Function
        8. 9.3.2.8  High-Speed Mode (HS)
        9. 9.3.2.9  Coexists in I3C Mixed Fast Mode
        10. 9.3.2.10 Time-Out Function
      3. 9.3.3 Timing Diagrams
      4. 9.3.4 Two-Wire Timing Diagrams
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode (SD)
      2. 9.4.2 One-Shot Mode (OS)
      3. 9.4.3 Continuous Conversion Mode (CC)
      4. 9.4.4 Thermostat Mode (TM)
        1. 9.4.4.1 Comparator Mode (TM = 0)
        2. 9.4.4.2 Interrupt Mode (TM = 1)
        3. 9.4.4.3 Polarity Mode (POL)
    5. 9.5 Register Map
      1. 9.5.1 Register Descriptions
        1. 9.5.1.1 Temperature Register (address = 00h) [default reset = 0000h]
        2. 9.5.1.2 Configuration Register (address = 01h) [default reset = 00FFh (60A0h TMP1075N)]
        3. 9.5.1.3 Low Limit Register (address = 02h) [default reset = 4B00h]
        4. 9.5.1.4 High Limit Register (address = 03h) [default reset = 5000h]
        5. 9.5.1.5 Device ID Register (address = 0Fh) [default reset = 7500]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Migrating From the xx75 Device Family
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 サポート・リソース
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.7 Timing Requirements:TMP1075

minimum and maximum specifications are over –55°C to 125°C and V+ = 1.7 V to 5.5 V (unless otherwise noted)(1)
FAST MODE HIGH-SPEED MODE UNIT
MIN MAX MIN MAX
f(SCL) SCL operating frequency 0.001 0.4 0.001 2.56 MHz
t(BUF) Bus-free time between STOP and START conditions 1300 160 ns
t(HDSTA) Hold time after repeated START condition.
After this period, the first clock is generated.		 600 160 ns
t(SUSTA) Repeated START condition setup time 600 160 ns
t(SUSTO) STOP condition setup time 600 160 ns
t(HDDAT) Data hold time(2) 0 0 130 ns
t(SUDAT) Data setup time 100 20 ns
t(LOW) SCL clock low period 1300 250 ns
t(HIGH) SCL clock high period 600 60 ns
t(VDAT) Data valid time (data response time)(3) 900 130 ns
tFDA Data fall time 300 100 ns
tR Clock rise time 300 40 ns
tF Clock fall time 300 40 ns
ttimeout Timeout (SCL = SDA = GND) 20 30 20 30 ms
tRC Clock/ data rise time for SCL = 100 kHz 1000 ns
(1) The host and device have the same V+ value. Values are based on statistical analysis of samples tested during initial release.
(2) The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time.
(3) t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse). = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).