JAJSFZ4E March   2009  – August 2018 TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28344 , TMS320C28345 , TMS320C28346

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings – Automotive
    3. 5.3 ESD Ratings – Commercial
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Consumption Summary
      1. Table 5-1 TMS320C28346/C28344 Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
      2. Table 5-2 TMS320C28345/C28343 Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
      3. 5.5.1     Reducing Current Consumption
    6. 5.6 Electrical Characteristics
    7. 5.7 Thermal Resistance Characteristics
      1. 5.7.1 ZHH Package
      2. 5.7.2 ZFE Package
    8. 5.8 Thermal Design Considerations
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-4 Clocking and Nomenclature (300-MHz Devices)
          2. Table 5-5 Clocking and Nomenclature (200-MHz Devices)
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-6 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-7 XCLKIN/X1 Timing Requirements – PLL Enabled
        2. Table 5-8 XCLKIN/X1 Timing Requirements – PLL Disabled
        3. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-10 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-11 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-12 IDLE Mode Timing Requirements
            2. Table 5-13 IDLE Mode Switching Characteristics
            3. Table 5-14 STANDBY Mode Timing Requirements
            4. Table 5-15 STANDBY Mode Switching Characteristics
            5. Table 5-16 HALT Mode Timing Requirements
            6. Table 5-17 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-18 ePWM Timing Requirements
            2. Table 5-19 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-20 Trip-Zone Input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-21 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
          4. 5.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. Table 5-22 Enhanced Capture (eCAP) Timing Requirements
            2. Table 5-23 eCAP Switching Characteristics
          5. 5.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. Table 5-24 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. Table 5-25 eQEP Switching Characteristics
          6. 5.9.4.2.6 ADC Start-of-Conversion Timing
            1. Table 5-26 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-27 External Interrupt Timing Requirements
          2. Table 5-28 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-29 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 5.9.4.5.1 Master Mode Timing
            1. Table 5-30 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-31 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.9.4.5.2 Slave Mode Timing
            1. Table 5-32 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-33 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.9.4.6.1 McBSP Transmit and Receive Timing
            1. Table 5-34 McBSP Timing Requirements
            2. Table 5-35 McBSP Switching Characteristics
          2. 5.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. Table 5-36 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-37 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-38 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-39 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-40 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-41 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-42 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-43 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 5.9.5 Emulator Connection Without Signal Buffering for the MCU
      6. 5.9.6 External Interface (XINTF) Timing
        1. 5.9.6.1 USEREADY = 0
        2. 5.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 5.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 5.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 5.9.6.5 External Interface Read Timing
          1. Table 5-46 External Interface Read Timing Requirements
          2. Table 5-47 External Interface Read Switching Characteristics
        6. 5.9.6.6 External Interface Write Timing
          1. Table 5-48 External Interface Write Switching Characteristics
        7. 5.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-49 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. Table 5-50 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. Table 5-51 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. Table 5-52 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 5.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-53 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. Table 5-54 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. Table 5-55 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 5.9.6.9 XHOLD and XHOLDA Timing
          1. Table 5-56 XHOLD/XHOLDA Timing Requirements
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF)
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
      8. 6.1.8  Boot ROM
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1–XINT7, XNMI)
      12. 6.1.12 Oscillator and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-Power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1  DMA Overview
      2. 6.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 6.2.3  Enhanced PWM Modules
      4. 6.2.4  High-Resolution PWM (HRPWM)
      5. 6.2.5  Enhanced CAP Modules
      6. 6.2.6  Enhanced QEP Modules
      7. 6.2.7  External ADC Interface
      8. 6.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 6.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 6.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 6.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
      12. 6.2.12 Inter-Integrated Circuit (I2C)
      13. 6.2.13 GPIO MUX
      14. 6.2.14 External Interface (XINTF)
    3. 6.3 Memory Maps
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスおよび開発ツールの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZFE|256
サーマルパッド・メカニカル・データ
発注情報

6.2.12 Inter-Integrated Circuit (I2C)

The device contains one I2C Serial Port. Figure 6-15 shows how the I2C peripheral module interfaces within the device.

TMS320C28346 TMS320C28345 TMS320C28344 TMS320C28343 TMS320C28342 TMS320C28341 i2cmod_prs439.gif
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCR0 register turns off the clock to the I2C port for low power operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 6-15 I2C Peripheral Module Interfaces

The I2C module has the following features:

  • Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
    • Support for 1-bit to 8-bit format transfers
    • 7-bit and 10-bit addressing modes
    • General call
    • START byte mode
    • Support for multiple master-transmitters and slave-receivers
    • Support for multiple slave-transmitters and master-receivers
    • Combined master transmit/receive and receive/transmit mode
    • Data transfer rate from 10 kbps up to 400 kbps (I2C Fast-mode rate)
  • One 16-word receive FIFO and one 16-word transmit FIFO
  • One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions:
    • Transmit-data ready
    • Receive-data ready
    • Register-access ready
    • No-acknowledgment received
    • Arbitration lost
    • Stop condition detected
    • Addressed as slave
  • An additional interrupt that can be used by the CPU when in FIFO mode
  • Module-enable and module-disable capability
  • Free data format mode

The registers in Table 6-16 configure and control the I2C port operation.

Table 6-16 I2C-A Registers

NAME ADDRESS DESCRIPTION
I2COAR 0x7900 I2C own address register
I2CIER 0x7901 I2C interrupt enable register
I2CSTR 0x7902 I2C status register
I2CCLKL 0x7903 I2C clock low-time divider register
I2CCLKH 0x7904 I2C clock high-time divider register
I2CCNT 0x7905 I2C data count register
I2CDRR 0x7906 I2C data receive register
I2CSAR 0x7907 I2C slave address register
I2CDXR 0x7908 I2C data transmit register
I2CMDR 0x7909 I2C mode register
I2CISRC 0x790A I2C interrupt source register
I2CPSC 0x790C I2C prescaler register
I2CFFTX 0x7920 I2C FIFO transmit register
I2CFFRX 0x7921 I2C FIFO receive register
I2CRSR – I2C receive shift register (not accessible to the CPU)
I2CXSR – I2C transmit shift register (not accessible to the CPU)