SPRS727C Data sheet

SPRS727C August 2012 – April 2014 TMS320C5517

PRODUCTION DATA.

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ZCH|196

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発注情報

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the bottom view of the package pin assignments.

Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

Figure 4-1 Pin Diagram

4.2 Signal Descriptions

The signal descriptions tables (Table 4-1 through Table 4-19) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors or bus-holders, and a functional pin description. For more information on pin multiplexing, see Section 4.3, Pin Multiplexing.

For proper device operation, external pullup and pulldown resistors may be required on some pins. Section 5.7.20.1.1, Pullup and Pulldown Resistors discusses situations where external pullup and pulldown resistors are required.

4.2.1 Oscillator and PLL

Table 4-1 Oscillator and PLL Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
CLKOUT	A7	O/Z	IPD DV_DDIO BH	DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap different clocks within the system clock generator. The CLKOUT_SRC bits in the CLKOUT Configuration Register (CLKOUTCR) can be used to specify the CLKOUT pin source. Additionally, the slew rate of the CLKOUT pin can be controlled by the Output Slew Rate Control Register (OSRCR) [0x1C16]. The output driver of the CLKOUT pin is enabled and disabled through the CLKOFF bit in the CPU ST3_55 register. When disabled, the CLKOUT pin's output driver is placed in high-impedance (Hi-Z) and the IPD is automatically enabled. When enabled, the output driver of the pin is enabled and the IPD is automatically disabled. At reset the CLKOUT pin is enabled until the beginning of the boot sequence, at which point the on-chip Bootloader sets CLKOFF = 1 and the CLKOUT pin is disabled (Hi-Z). For more information on the ST3_55 register, see the C55x 3.0 CPU Reference Guide [literature number: SWPU073]. The IPD resistor on this pin is enabled when CLKOUT is in Hi-Z state.
CLKIN	A8	I	IPD DV_DDIO BH	Input clock. This signal is used to input an external clock when the 12-MHz on-chip USB oscillator is not used as the system clock (CLK_SEL = 1). To appropriately set the various serial port frequencies during bootloading, the bootloader ROM code assumes CLKIN is running at the frequency indicated by the setting (see Section 6.4, Boot Modes, for the supported frequencies and details about the bootmode). The CLK_SEL pin selects the source for the system clock generator, with the options being the USB oscillator (CLK_SEL=0) or CLKIN (CLK_SEL=1) pins. When the CLK_SEL pin is low, this pin should be tied to ground (V_SS). When CLK_SEL is high, this pin should be driven by an external clock source. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD disabled at reset.
CLK_SEL	C7	I	– DV_DDIO BH	Clock input select. This pin selects between the on-chip USB oscillator or CLKIN. 0 = The on-chip USB oscillator is enabled at reset and drives the system clock generator. The CLKIN is ignored. Also, the USB LDOO is enabled at reset (USB_LDO_EN=1). The on-chip USB oscillator and USB_LDO cannot be disabled if CLK_SEL=0. 1 = CLKIN drives the system clock generator. The on-chip USB oscillator and USB LDO are disabled at reset (USB_LDO_EN=1), but they can be enabled by software. This pin is not allowed to change during device operation; it must be tied high or low at the board.
V_{DDA_PLL}	C10	PWR	see Section 5.2, ROC	1.3-V Analog PLL power supply for the system clock generator. This supply pin must not be connected to ANA_LDOO pin. The supply pin must be externally powered.
V_{SSA_PLL}	D9	GND	see Section 5.2, ROC	Analog PLL ground for the system clock generator.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal

(4) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current. Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.

4.2.2 Real-Time Clock (RTC)

Table 4-2 RTC Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
RTC_XO	A9	O/Z	– CV_DDRTC DV_DDRTC	Real-time clock oscillator output. This pin operates at the RTC core voltage, CV_DDRTC, and supports a 32.768-kHz crystal. If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to CV_DDRTC and RTC_XO to ground (V_SS). A voltage must still be applied to CV_DDRTCby an external power source (see Section 5.2, Recommended Operating Conditions). None of the on-chip LDOs can power CV_DDRTC. Note: When RTC oscillator is disabled, the RTC registers (I/O address range 1900h – 197Fh) are not accessible.
RTC_XI	B9	I	– CV_DDRTC DV_DDRTC	Real-time clock oscillator input. If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to CV_DDRTC and RTC_XO to ground (V_SS). A voltage must still be applied to CV_DDRTCby an external power source (see Section 5.2, Recommended Operating Conditions). None of the on-chip LDOs can power CV_DDRTC. Note: When RTC oscillator is disabled, the RTC registers (I/O address range 1900h – 197Fh) are not accessible.
RTC_CLKOUT	D8	O/Z	– DV_DDRTC	Real-time clock output pin. This pin operates at DV_DDRTC voltage. The RTC_CLKOUT pin is enabled and disabled through the RTCCLKOUTEN bit in the RTC Power Management Register (RTCPMGT). At reset, the RTC_CLKOUT pin is disabled (high-impedance [Hi-Z]).
WAKEUP	E8	I/O/Z	– DV_DDRTC	The active-high pin is used to WAKEUP the core from idle condition. This pin defaults to an input at CV_DDRTC powerup, but can also be configured as an active-low open-drain output signal to wakeup an external device from an RTC alarm.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

4.2.3 RESET, Interrupts, and JTAG

Table 4-3 RESET, Interrupts, and JTAG Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
RESET
XF	M8	O/Z	IPU DV_DDIO BH	External Flag Output. XF is used for signaling other processors in multiprocessor configurations or XF can be used as a fast general-purpose output pin. XF is set high by the BSET XF instruction and XF is set low by the BCLR XF instruction or by writing to bit 13 of the ST1_55 register. For more information on the ST1_55 register, see the C55x 3.0 CPU Reference Guide [literature number: SWPU073]. For the XF pin's states after reset, see Figure 5-9, BootMode Latching. XF pin can manually configured as Hi-Z state only in boundary-scan mode. When this pin is in Hi-Z state, the IPU is enabled. The IPU on this pin is disabled at reset.
RESET	D6	I	IPU DV_DDIO BH	Device reset. RESET causes the DSP to terminate execution and loads the program counter with the contents of the reset vector. When RESET is brought to a high level, the reset vector in ROM at FFFF00h forces the program execution to branch to the location of the on-chip ROM bootloader. RESET affects the various registers and status bits. The IPU resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h). The IPU is disabled at reset.
JTAG
For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference [literature number: SPRU589].
TMS	L8	I	IPU DV_DDIO BH	IEEE standard 1149.1 test mode select. This serial control input is clocked into the TAP controller on the rising edge of TCK. If the emulation header is located greater than 6 inches from the device, TMS must be buffered. In this case, the input buffer for TMS needs a pullup resistor connected to DV_DDIO to hold the signal at a known value when the emulator is not connected. A resistor value of 4.7 kΩ or greater is suggested. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference [literature number: SPRU589]. The IPU resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPU is enabled at reset.
TDO	M7	I/O/Z	IPU DV_DDIO BH	IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance (Hi-Z) state except when the scanning of data is in progress. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference [literature number: SPRU589]. If the emulation header is located greater than 6 inches from the device, TDO must be buffered. Despite the fact that the IEEE 1149.1 (JTAG) standard defines the TDO pin as a 3-state output (O/Z), this device has a bidirectional IO-cell. The bidirectional cell's input buffer is used for non-JTAG production test purposes. To achieve the lowest power, this input buffer must not be allowed to float. The IEEE standard defines the pin as tri-stated in the Test-Logic-Reset state and our device obeys that requirement. Therefore, to achieve the lowest power the IPU should remain enabled. The IPU resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPU is enabled at reset.
TDI	L7	I	IPU DV_DDIO BH	IEEE standard 1149.1 test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. If the emulation header is located greater than 6 inches from the device, TDI must be buffered. In this case, the input buffer for TDI needs a pullup resistor connected to DV_DDIO to hold this signal at a known value when the emulator is not connected. A resistor value of 4.7 kΩ or greater is suggested. The IPU resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPU is enabled at reset.
TCK	M6	I	IPU DV_DDIO BH	IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. If the emulation header is located greater than 6 inches from the device, TCK must be buffered. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference [literature number: SPRU589]. The IPU resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPU is enabled at reset.
TRST	M9	I	IPD DV_DDIO BH	IEEE standard 1149.1 reset signal for test and emulation logic. TRST, when high, allows the IEEE standard 1149.1 scan and emulation logic to take control of the operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. The device will not operate properly if this reset pin is never asserted low. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference [literature number: SPRU589]. It is recommended that an external pulldown resistor be used in addition to the IPD -- especially if there is a long trace to an emulation header. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is enabled at reset.
EMU1	M5	I/O/Z	IPU DV_DDIO BH	Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator system and is defined as input/output by way of the emulation logic. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference [literature number: SPRU589]. An external pullup to DV_DDIO is required to provide a signal rise time of less than 10 µsec. A 4.7-kΩ resistor is suggested for most applications. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference [literature number: SPRU589]. The IPU resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPU is enabled at reset.
EMU0	L6	I/O/Z	IPU DV_DDIO BH	Emulator 0 pin. When TRST is driven low and then high, the state of the EMU0 pin is latched and used to connect the JTAG pins (TCK, TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when the latched value of EMU0 = 0) or to the DSP Emulation TAP (when the latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the emulation logic. An external pullup to DV_DDIO is required to provide a signal rise time of less than 10 µsec. A 4.7-kΩ resistor is suggested for most applications. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference [literature number: SPRU589]. The IPU resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPU is enabled at reset.
EXTERNAL INTERRUPTS
INT1	E7	I	IPU DV_DDIO BH	External interrupt inputs (INT1 and INT0). These pins are maskable via their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt mode bit. The pins can be polled and reset by their specific Interrupt Flag Register (IFR1, IFR0). The IPU resistor on these pins can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPU is disabled at reset.
INT0	C6	I	IPU DV_DDIO BH

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

4.2.4 External Memory Interface (EMIF)

Table 4-4 EMIF Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME⁽⁵⁾	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
EMIF FUNCTIONAL PINS: ASYNC (NOR, SRAM, and NAND)
				Note: When accessing 8-bit Asynchronous memory: Connect EM_A[20:0] to memory address pins [22:2] Connect EM_BA[1:0] to memory address pins [1:0] For 16-bit Asynchronous memory: Connect EM_A[20:1] to memory address pins [20:1] Connect EM_BA[1] to memory address pin [0]
GP[26]/ EM_A[20]	J3	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 20. Mux control via the A20_MODE bit in the EBSR (see Figure 5-10). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
GP[25]/ EM_A[19]	G4	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 19. Mux control via the A19_MODE bit in the EBSR (see Figure 5-10). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
GP[24]/ EM_A[18]	G2	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 18. Mux control via the A18_MODE bit in the EBSR (see Figure 5-10). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
GP[23]/ EM_A[17]	F2	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 17. Mux control via the A17_MODE bit in the EBSR (see Figure 5-10). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
GP[22]/ EM_A[16]	E2	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 16. Mux control via the A16_MODE bit in the EBSR (see Figure 5-10). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
GP[21]/ EM_A[15]	N1	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 15. Mux control via the A15_MODE bit in the EBSR (see Figure 5-10). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
EM_A[14]	M1	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 14. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[13]	L1	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 13. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[12]/ (CLE)	K1	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 12. When interfacing with NAND Flash, this pin also acts as Command Latch Enable (CLE). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[11]/ (ALE)	K2	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 11. When interfacing with NAND Flash, this pin also acts as Address Latch Enable (ALE). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[10]	L2	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 10. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[9]	J2	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 9. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[8]	J1	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 8. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[7]	H2	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 7. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[6]	F1	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 6. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[5]	D1	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 5. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[4]	C1	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 4. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[3]	D2	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 3. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[2]	E1	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 2. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[1]	C2	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 1. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_A[0]	B2	I/O/Z	IPD DV_DDEMIF BH	This pin is the EMIF external address pin 0. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5 (1C4Dh) register. The IPD is disabled at reset.
EM_D[15]	J4	I/O/Z	IPD DV_DDEMIF BH	EMIF 16-bit bidirectional bus. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR4 (1C4Ch) register. The IPD is disabled at reset.
EM_D[14]	K3
EM_D[13]	K4
EM_D[12]	L3
EM_D[11]	C4
EM_D[10]	D3
EM_D[9]	F4
EM_D[8]	E3
EM_D[7]	H3
EM_D[6]	K5
EM_D[5]	M2
EM_D[4]	L4
EM_D[3]	D4
EM_D[2]	F3
EM_D[1]	E5
EM_D[0]	G3
EM_CS5	A3	O/Z	IPD DV_DDEMIF BH	EMIF chip select 5 output for use with asynchronous memories (that is, NOR flash, NAND flash, or SRAM). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is disabled at reset.
EM_CS4	C3	O/Z	IPD DV_DDEMIF BH	EMIF chip select 4 output for use with asynchronous memories (that is, NOR flash, NAND flash, or SRAM). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is disabled at reset.
EM_CS3	M4	O/Z	IPD DV_DDEMIF BH	EMIF NAND chip select 3 output for use with asynchronous memories (that is, NOR flash, NAND flash, or SRAM). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is disabled at reset.
EM_CS2	C5	O/Z	IPD DV_DDEMIF BH	EMIF NAND chip select 2 output for use with asynchronous memories (that is, NOR flash, NAND flash, or SRAM). The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is disabled at reset.
EM_WE	H1	O/Z	IPD DV_DDEMIF BH	EMIF asynchronous memory write enable output The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is disabled at reset.
EM_OE	E4	O/Z	IPD DV_DDEMIF BH	EMIF asynchronous memory read enable output The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is disabled at reset.
EM_R/W	B6	O/Z	IPD DV_DDEMIF BH	EMIF asynchronous read and write output The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is disabled at reset.
EM_DQM1/ UHPI_HBE1	P1	I/O/Z	IPD DV_DDEMIF BH	These pins are multiplexed between EMIF and UHPI. For EMIF, asynchronous data write strobes and byte enables or EMIF SDRAM and mSDRAM data mask bits. Mux control via the PPMODE bits in the EBSR. The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is disabled at reset.
EM_DQM0/ UHPI_HBE0	B5	I/O/Z	IPD DV_DDEMIF BH
EM_BA[1]	B1	O/Z	IPD DV_DDEMIF BH	EMIF asynchronous bank address 16-bit wide memory: EM_BA[1] forms the device address[0] and BA[0] forms device address [23]. 8-bit wide memory: EM_BA[1] forms the device address[1] and BA[0] forms device address [0]. EMIF SDRAM and mSDRAM bank address. The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is disabled at reset.
EM_BA[0]	A1	O/Z	IPD DV_DDEMIF BH
EM_WAIT5	H4	I	IPD DV_DDEMIF BH	EMIF wait state extension input 5 for EM_CS5 The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is enabled at reset.
EM_WAIT4	G1	I	IPD DV_DDEMIF BH	EMIF wait state extension input 4 for EM_CS4 The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is enabled at reset.
EM_WAIT3	K6	I	IPD DV_DDEMIF BH	EMIF wait state extension input 3 for EM_CS3 The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is enabled at reset.
EM_WAIT2	D5	I	IPD DV_DDEMIF BH	EMIF wait state extension input 2 for EM_CS2 The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is enabled at reset.
EMIF FUNCTIONAL PINS: SDRAM and mSDRAM ONLY
EM_CS1/ UHPI_HDS2	A4	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM chip select 1 output Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
EM_CS0/ UHPI_HDS1	B3	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM chip select 0 output Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register.
EM_SDCLK	M3	O/Z	IPD DV_DDEMIF BH	EMIF SDRAM and mSDRAM clock The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
EM_SDCKE/ UHPI_HHWIL	N2	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM clock enable Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
EM_SDRAS/ UHPI_HAS	A6	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM row address strobe Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
EM_SDCAS/ UHPI_HCS	B4	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM column strobe Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

4.2.5 Inter-Integrated Circuit (I2C)

Table 4-5 Inter-Integrated Circuit (I2C) Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
I2C
SCL	B7	I/O/Z	– DV_DDIO BH	This pin is the I2C clock output. Per the I2C standard, an external pullup is required on this pin.
SDA	B8	I/O/Z	– DV_DDIO BH	This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup is required on this pin.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

4.2.6 Inter-IC Sound (I2S)

Table 4-6 Inter-IC Sound (I2S0, I2S2, and I2S3) Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME⁽⁵⁾	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
Interface 0 (I2S0)
MMC0_D0/ I2S0_DX/ GP[2]/ McBSP_DX	L9	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP and GPIO. For I2S, it is I2S0 transmit data output I2S0_DX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_CLK/ I2S0_CLK/ GP[0]/ McBSP_CLKX	L10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP and GPIO. For I2S, it is I2S0 clock input/output I2S0_CLK. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D1/ I2S0_RX/ GP[3]/ McBSP_DR	M10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP and GPIO. For I2S, it is I2S0 receive data input I2S0_RX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_CMD/ I2S0_FS/ GP[1]/ McBSP_FSX	M11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP and GPIO. For I2S, it is I2S0 frame synchronization input/output I2S0_FS. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
Interface 1 (I2S2)
I2S2_DX/ UHPI_HD[11]/ GP[27]/ SPI_TX	P12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO, and SPI. For I2S, it is I2S2 transmit data output I2S2_DX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.
I2S2_CLK/ UHPI_HD[8]/ GP[18]/ SPI_CLK	N10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO, and SPI. For I2S, it is I2S2 clock input/output I2S2_CLK. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
I2S2_RX/ UHPI_HD[10]/ GP[20]/ SPI_RX	N11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI, I2S2, GPIO, and SPI. For I2S, it is I2S2 receive data input I2S2_RX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
I2S2_FS/ UHPI_HD[9]/ GP[19]/ SPI_CS0	P11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO, and SPI. For I2S, it is I2S2 frame synchronization input/output I2S2_FS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
Interface 2 (I2S3)
UART_TXD/ UHPI_HD[15]/ GP[31]/ I2S3_DX	P14	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. For I2S, it is I2S3 transmit data output I2S3_DX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.
UART_RTS/ UHPI_HD[12]/ GP[28]/ I2S3_CLK	N12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. For I2S, it is I2S3 clock input/output I2S3_CLK. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.
UART_RXD/ UHPI_HD[14]/ GP[30]/ I2S3_RX	N13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. For I2S, it is I2S3 receive data input I2S3_RX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
UART_CTS/ UHPI_HD[13]/ GP[29]/ I2S3_FS	P13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed betweenUART, UHPI, GPIO, and I2S3. For I2S, it is I2S3 frame synchronization input/output I2S3_FS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

4.2.7 Multichannel Buffered Serial Port (McBSP)

Table 4-7 McBSP Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME⁽⁵⁾	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
McBSP
MMC0_CLK/ I2S0_CLK/ GP[0]/ McBSP_CLKX	L10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP and GPIO. For McBSP, this is the McBSP transmit clock, McBSP_CLKX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_CMD/ I2S0_FS/ GP[1]/ McBSP_FSX	M11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP and GPIO. For McBSP, this is the McBSP transmit frame sync, McBSP_FSX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D0/ I2S0_DX/ GP[2]/ McBSP_DX	L9	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP and GPIO. For McBSP, this is the McBSP transmit data , McBSP_DX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D1/ I2S0_RX/ GP[3]/ McBSP_DR	M10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP and GPIO. For McBSP, this is the McBSP receive data, McBSP_RX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D2/ GP[4]/ McBSP_FSR	L12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, McBSP and GPIO. For McBSP, this is the McBSP receive frame sync, McBSP_FSR. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D3/ GP[5]/ McBSP_CLKR_ CLKS	L11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, McBSP and GPIO. For McBSP, this is the McBSP receive clock, McBSP_CLKR or the McBSP sample rate generator clock input, McBSP_CLKS. The bit 15 of EBSR register determines this port to be McBSP_CLKR or McBSP_CLKS. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

4.2.8 Multichannel Serial Port Interface (McSPI)

Table 4-8 McSPI Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME⁽⁵⁾	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
McSPI
MMC1_CLK/ McSPI_CLK/ GP[6]	M13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI and GPIO. For McSPI, this is the McSPI data clock, McSPI_CLK. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_CMD/ McSPI_CS0/ GP[7]	L14	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI and GPIO. For McSPI, this is the McSPI chip select 0 signal, McSPI_CS0. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_D0/ McSPI_SIMO/ GP[8]	M14	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI and GPIO. For McSPI, this is the McSPI data, McSPI_SIMO (Slave Input Master Output). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_D1/ McSPI_SOMI/ GP[9]	M12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI and GPIO. For McSPI, this is the McSPI data, McSPI_SOMI (Slave Output Master Input). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_D2/ McSPI_CS1/ GP[10]	K14	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI and GPIO. For McSPI, this is the McSPI chip select 1 signal, McSPI_CS1. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_D3/ McSPI_CS2/ GP[11]	L13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI and GPIO. For McSPI, this is the McSPI chip select 2 signal, McSPI_CS2. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

4.2.9 Serial Peripheral Interface (SPI)

Table 4-9 SPI Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME⁽⁵⁾	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
Serial Port Interface (SPI)
SPI_CS0/ UHPI_HCNTL0	P4	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and SPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS0. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
I2S2_FS/ UHPI_HD[9]/ GP[19]/ SPI_CS0	P11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO, and SPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS0. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
SPI_CS1/ UHPI_HCNTL1	N4	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between SPI and UHPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS1. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
SPI_CS2/ UHPI_HR_NW	P5	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between SPI and UHPI. For SPI, this pin is SPI chip select SPI_CS2. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
SPI_CS3/ UHPI_HRDY	N5	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between SPI and UHPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS3. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
SPI_CLK/ UHPI_HINT	N3	O/Z	IPD DV_DDIO BH	This pin is multiplexed between SPI and UHPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is clock output SPI_CLK. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
I2S2_CLK/ UHPI_HD[8]/ GP[18]/ SPI_CLK	N10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO, and SPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is clock output SPI_CLK. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
SPI_TX/ UHPI_HD[1]	N6	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and SPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI transmit data output. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
I2S2_DX/ UHPI_HD[11]/ GP[27]/ SPI_TX	P12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO, and SPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI transmit data output. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.
SPI_RX/ UHPI_HD[0]	P6	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between SPI and UHPI. Mux control via the PPMODE bits in the EBSR. For SPI this pin is SPI receive data input. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
I2S2_RX/ UHPI_HD[10]/ GP[20]/ SPI_RX	N11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO, and SPI. Mux control via the PPMODE bits in the EBSR. For SPI this pin is SPI receive data input. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

4.2.10 Universal Asynchronous Receiver and Transmitter (UART)

Table 4-10 UART Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME⁽⁵⁾	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
UART
UART_RXD/ UHPI_HD[14]/ GP[30]/ I2S3_RX	N13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. When used by UART, it is the receive data input UART_RXD. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
UART_TXD/ UHPI_HD[15]/ GP[31]/ I2S3_DX	P14	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. In UART mode, it is the transmit data output UART_TXD. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.
UART_CTS/ UHPI_HD[13]/ GP[29]/ I2S3_FS	P13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. In UART mode, it is the clear to send input UART_CTS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
UART_RTS/ UHPI_HD[12]/ GP[28]/ I2S3_CLK	N12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. In UART mode, it is the ready to send output UART_RTS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

4.2.11 Universal Serial Bus (USB) 2.0

Table 4-11 USB2.0 Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
USB 2.0
USB_MXI	G13	I	USB_V_DDOSC	12-MHz crystal oscillator input used for the USB subsystem and optionally for the system clock generator. If CLK_SEL=0, the USB oscillator is enabled at reset and is used as the clock source for the system clock generator. In this configuration (CLK_SEL=0), the USB oscillator cannot be disabled. If CLK_SEL=1, the USB oscillator is disabled at reset and the CLKIN pin is used as the source for the system clock generator. In this configuration (CLK_SEL=1), the USB oscillator can be enabled or disabled via software. When using an external 12-MHz oscillator, the external oscillator clock signal should be connected to the USB_MXI pin and the amplitude of the oscillator clock signal must meet the V_IH requirement (see Section 5.2, Recommended Operating Conditions). The USB_MXO is left unconnected and the USB_V_SSOSC signal is connected to board ground (V_SS).
USB_MXO	G14	O	USB_V_DDOSC	12-MHz crystal oscillator output used for the USB subsystem and optionally for the system clock generator. If CLK_SEL=0, the USB oscillator is enabled at reset and is used as the clock source for the system clock generator. In this configuration (CLK_SEL=0), the USB oscillator cannot be disabled. If CLK_SEL=1, the USB oscillator is disabled at reset and the CLKIN pin is used as the source for the system clock generator. In this configuration (CLK_SEL=1), the USB oscillator can be enabled or disabled via software. When using an external 12-MHz oscillator, the external oscillator clock signal should be connected to the USB_MXI pin and the amplitude of the oscillator clock signal must meet the V_IH requirement (see Section 5.2, Recommended Operating Conditions). The USB_MXO is left unconnected and the USB_V_SSOSC signal is connected to board ground (V_SS).
USB_V_DDOSC	G12	S	see Section 5.2, ROC	3.3-V power supply for USB oscillator. When the USB peripheral is not used, USB_V_DDOSC should be connected to ground (V_SS).
USB_V_SSOSC	F11	S	see Section 5.2, ROC	Ground for USB oscillator. When using a 12-MHz crystal, this pin is a local ground for the crystal and must not be connected to the board ground (See Figure 5-11). When using an external 12-MHz oscillator, the external oscillator clock signal should be connected to the USB_MXI pin and the amplitude of the oscillator clock signal must meet the V_IH requirement (see Section 5.2, Recommended Operating Conditions). The USB_MXO is left unconnected and the USB_V_SSOSC signal is connected to board ground (V_SS).
USB_VBUS	J12	A	see Section 5.2, ROC	USB power detect. 5-V input that signifies that VBUS is connected. This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply Sequencing. When the USB peripheral is not used, the USB_VBUS signal should be connected to ground (V_SS).
USB_DP	H14	A I/O	USB_V_DDA3P3	USB bidirectional Data Differential signal pair [positive and negative]. When the USB peripheral is not used, the USB_DP and USB_DM signals should both be tied to ground (V_SS).
USB_DM	J14	A I/O	USB_V_DDA3P3
USB_R1	G9	A I/O	USB_V_DDA3P3	External resistor connect. Reference current output. This pin must be connected via a 10-kΩ ±1% resistor to USB_V_SSREF and be placed as close to the device as possible. When the USB peripheral is not used, the USB_R1 signal should be connected via a 10-kΩ resistor to USB_V_SSREF.
USB_V_SSREF	G10	GND	see Section 5.2, ROC	Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to USB_R1. When the USB peripheral is not used, the USB_V_SSREF signal should be connected directly to ground (V_ss).
USB_V_DDA3P3	H12	S	see Section 5.2, ROC	Analog 3.3 V power supply for USB PHY. This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply Sequencing. When the USB peripheral is not used, the USB_V_DDA3P3 signal should be connected to ground (V_SS).
USB_V_SSA3P3	H11	GND	see Section 5.2, ROC	Analog ground for USB PHY.
USB_V_DDA1P3	H10	S	see Section 5.2, ROC	Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits] This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply Sequencing. When the USB peripheral is not used, the USB_V_DDA1P3 signal should be connected to ground (V_SS).
USB_V_SSA1P3	H9	GND	see Section 5.2, ROC	Analog ground for USB PHY [For high speed sensitive analog circuits].
USB_V_DD1P3	J13	S	see Section 5.2, ROC	1.3-V digital core power supply for USB PHY. This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply Sequencing. When the USB peripheral is not used, the USB_V_DD1P3 signal should be connected to ground (V_SS).
USB_V_SS1P3	H13	GND	see Section 5.2, ROC	Digital core ground for USB PHY.
USB_V_DDPLL	G8	S	see Section 5.2, ROC	3.3 V USB Analog PLL power supply. Care should be taken to prevent noise on this supply. Consider using a ferrite bead if the power supply for this pin is shared with digital logic. See the Filtering Techniques Application Report [literature number: SCAA048] for more information. When the USB peripheral is not used, the USB_V_DDPLL signal should be connected to ground (V_SS).
USB_V_SSPLL	G11	GND	see Section 5.2, ROC	USB Analog PLL ground.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

4.2.12 Universal Host-Port Interface (UHPI)

Table 4-12 UHPI Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME⁽⁵⁾	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
SPI_CLK/ UHPI_HINT	N3	O/Z	IPD DV_DDIO BH	This pin is multiplexed between SPI and UHPI. For UHPI, this pin is UHPI host interrupt, UHPI_HINT. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
SPI_CS0/ UHPI_HCNTL0	P4	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between SPI and UHPI. For UHPI, this pin is UHPI access control, UHPI_HCNTL0. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
SPI_CS1/ UHPI_HCNTL1	N4	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between SPI and UHPI. For UHPI, this pin is UHPI access control, UHPI_HCNTL1. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
SPI_CS2/ UHPI_HR_NW	P5	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between SPI and UHPI. For UHPI this pin is UHPI read and write, UHPI_HR_NW. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
SPI_CS3/ UHPI_HRDY	N5	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between SPI and UHPI. For UHPI, this pin is the UHPI ready, UHPI_HRDY. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
UART_TXD/ UHPI_HD[15]/ GP[31]/ I2S3_DX	P14	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.
UART_RXD/ UHPI_HD[14]/ GP[30]/ I2S3_RX	N13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
UART_CTS/ UHPI_HD[13]/ GP[29]/ I2S3_FS	P13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
UART_RTS/ UHPI_HD[12]/ GP[28]/ I2S3_CLK	N12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.
I2S2_DX/ UHPI_HD[11]/ GP[27]/ SPI_TX	P12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.
I2S2_RX/ UHPI_HD[10]/ GP[20]/ SPI_RX	N11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
I2S2_FS/ UHPI_HD[9]/ GP[19]/ SPI_CS0	P11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
I2S2_CLK/ UHPI_HD[8]/ GP[18]/ SPI_CLK	N10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[17]/ UHPI_HD[7]	P10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[16]/ UHPI_HD[6]	N9	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[15]/ UHPI_HD[5]	P9	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[14]/ UHPI_HD[4]	N8	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[13]/ UHPI_HD[3]	N7	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[12]/ UHPI_HD[2]	P7	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and GPIO. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
SPI_TX/ UHPI_HD[1]	N6	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and SPI. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
SPI_RX/ UHPI_HD[0]	P6	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and SPI. For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
EM_DQM1/ UHPI_HBE1	P1	I/O/Z	IPD DV_DDIO BH	These two pins are multiplexed between UHPI and SDRAM. For UHPI, these two pins are UHPI Byte Enables, UHPI_HBE[1:0]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6 (1C4Fh) register. The IPD is disabled at reset.
EM_DQM0/ UHPI_HBE0	B5	I/O/Z	IPD DV_DDIO BH
EM_CS1/ UHPI_HDS2	A4	I/O/Z	IPD DV_DDIO BH	These two pins are multiplexed between UHPI and SDRAM. For UHPI, these two pins are UHPI data strobe pins, UHPI_HDS[2:1]. Mux control via the PPMODE bits in the EBSR. The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
EM_CS0/ UHPI_HDS1	B3	I/O/Z	IPD DV_DDIO BH
EM_SDCKE/ UHPI_HHWIL	N2	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and SDRAM. For UHPI, this pin is Half-word Identification control input pin, UHPI_HHWIL. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
EM_SDRAS/ UHPI_HAS	A6	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and SDRAM. For UHPI, this pin is address strobe pin, UHPI_HAS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.
EM_SDCAS/ UHPI_HCS	B4	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UHPI and SDRAM. For UHPI, this pin is chip select pin, UHPI_HCS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h) register. The IPD is disabled at reset.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

4.2.13 MultiMedia Card (MMC)

Table 4-13 MMC1 and SD Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME⁽⁵⁾	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
MMC and SD
MMC1_CLK/ McSPI_CLK/ GP[6]	M13	O	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI, and GPIO. For MMC and SD, this is the MMC1 data clock output MMC1_CLK. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_CMD/ McSPI_CS0/ GP[7]	L14	O	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI, and GPIO. For MMC and SD, this is the MMC1 command I/O output MMC1_CMD. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_D3/ McSPI_CS2/ GP[11]	L13	I/O/Z	IPD DV_DDIO BH	These pins are multiplexed between MMC1, McSPI, and GPIO. In MMC and SD mode, all these pins are the MMC1 nibble wide bidirectional data bus. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_D2/ McSPI_CS1/ GP[10]	K14	I/O/Z	IPD DV_DDIO BH
MMC1_D1/ McSPI_SOMI/ GP[9]	M12	I/O/Z	IPD DV_DDIO BH
MMC1_D0/ McSPI_SIMO/ GP[8]	M14	I/O/Z	IPD DV_DDIO BH

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

Table 4-14 MMC0 and SD Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME⁽⁵⁾	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
MMC and SD
MMC0_CLK/ I2S0_CLK/ GP[0]/ McBSP_CLKX	L10	O	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO. For MMC and SD, this is the MMC0 data clock output MMC0_CLK. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_CMD/ I2S0_FS/ GP[1]/ McBSP_FSX	M11	O	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO. For MMC and SD, this is the MMC0 command I/O output MMC0_CMD. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D3/ GP[5]/ McBSP_CLKR_ CLKS	L11	I/O/Z	IPD DV_DDIO BH	These pins are multiplexed between MMC0, I2S0, McBSP and GPIO In MMC and SD mode, these pins are the MMC0 nibble wide bidirectional data bus. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D2/ GP[4]/ McBSP_FSR	L12	I/O/Z	IPD DV_DDIO BH
MMC0_D1/ I2S0_RX/ GP[3]/ McBSP_DR	M10	I/O/Z	IPD DV_DDIO BH
MMC0_D0/ I2S0_DX/ GP[2]/ McBSP_DX	L9	I/O/Z	IPD DV_DDIO BH

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

4.2.14 Successive Approximation (SAR) Analog-to-Digital Converter (ADC)

Table 4-15 10-Bit SAR ADC Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
SAR ADC
GPAIN0	D10	I/O	V_{DDA_ANA}	GPAIN0: General -Purpose Output and Analog Input pin 0. This pin is demuxed internally into ADC Channels 0, 1, and 2. GPAIN0 can also be used as a general-purpose open-drain output. This pin is unique among the GPAIN pins in that it is the only pin that is 3.6 V-tolerant to support measuring a battery voltage. GPAIN0 can accommodate input voltages from 0 V to 3.6 V; although, the ADC is unable to accept signals greater than V_{DDA_ANA} without clamping. ADC Channel 1 is capable of switching in an internal resistor divider that has a divide ratio of approximately 1/8.
GPAIN1	A11	I/O	V_{DDA_ANA}	GPAIN1: General -Purpose Output and Analog Input pin 1. This pin is connected to ADC Channel 3. GPAIN1 can be used as a general-purpose output if certain requirements are met (see the following note). GPAIN1 can accommodate input voltages from 0 V to V_{DDA_ANA}. Note: If the ANA_LDO is used to supply power to V_{DDA_ANA}, this pin must not be used as a general-purpose output (driving high) since the max current capability (see the I_SD parameter in Section 5.3.2, Electrical Characteristics) of the ANA_LDO can be exceeded. Doing so may result in the on-chip power-on reset (POR) resetting the chip.
GPAIN2	B11	I/O	V_{DDA_ANA}	GPAIN2: General -Purpose Output and Analog Input pin 2. This pin is connected to ADC Channel 4. GPAIN2 can be used as a general-purpose output if certain requirements are met (see the following note). GPAIN2 can accommodate input voltages from 0 V to V_{DDA_ANA}. Note: If the ANA_LDO is used to supply power to V_{DDA_ANA}, this pin must not be used as a general-purpose output (driving high) since the max current capability (see the I_SD parameter in Section 5.3.2, Electrical Characteristics) of the ANA_LDO can be exceeded. Doing so may result in the on-chip POR resetting the chip.
GPAIN3	C11	I/O	V_{DDA_ANA}	GPAIN3: General -Purpose Output and Analog Input pin 3. This pin is connected to ADC Channel 5. GPAIN3 can be used as a general-purpose output if certain requirements are met (see the following note). GPAIN3 can accommodate input voltages from 0 V to V_{DDA_ANA}. Note: If the ANA_LDO is used to supply power to V_{DDA_ANA}, this pin must not be used as a general-purpose output (driving high) since the max current capability (see the I_SD parameter in Section 5.3.2, Electrical Characteristics) of the ANA_LDO can be exceeded. Doing so may result in the on-chip POR resetting the chip.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

4.2.15 General-Purpose Input and Output (GPIO)

Table 4-16 GPIO Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME⁽⁵⁾	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
General-Purpose Input/Output
XF	M8	O/Z	IPU DV_DDIO BH	External Flag Output. XF is used for signaling other processors in multiprocessor configurations or XF can be used as a fast general-purpose output pin. XF is set high by the BSET XF instruction and XF is set low by the BCLR XF instruction or by writing to bit 13 of the ST1_55 register. For more information on the ST1_55 register, see the C55x 3.0 CPU Reference Guide [literature number: SWPU073]. For the XF pin's states after reset, see Figure 5-9, BootMode Latching. XF pin can manually configured as Hi-Z state only in boundary-scan mode. When this pin is in Hi-Z state, the IPU is enabled. The IPU on this pin is disabled at reset.
MMC0_CLK/ I2S0_CLK/ GP[0]/ McBSP_CLKX	L10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO. For GPIO, it is general-purpose input/output pin 0 (GP[0]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_CMD/ I2S0_FS/ GP[1]/ McBSP_FSX	M11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO. For GPIO, it is general-purpose input/output pin 1 (GP[1]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D0/ I2S0_DX/ GP[2]/ McBSP_DX	L9	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO. For GPIO, it is general-purpose input/output pin 2 (GP[2]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D1/ I2S0_RX/ GP[3]/ McBSP_DR	M10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO. For GPIO, it is general-purpose input/output pin 3 (GP[3]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D2/ GP[4]/ McBSP_FSR	L12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, McBSP, and GPIO. For GPIO, it is general-purpose input/output pin 4 (GP[4]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC0_D3/ GP[5]/ McBSP_CLKR_ CLKS	L11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC0, McBSP, and GPIO. For GPIO, it is general-purpose input/output pin 5 (GP[5]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_CLK/ McSPI_CLK/ GP[6]	M13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI, and GPIO. For GPIO, it is general-purpose input/output pin 6 (GP[6]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_CMD/ McSPI_CS0/ GP[7]	L14	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI, and GPIO. For GPIO, it is general-purpose input/output pin 7 (GP[7]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_D0/ McSPI_SIMO/ GP[8]	M14	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI, and GPIO. For GPIO, it is general-purpose input/output pin 8 (GP[8]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_D1/ McSPI_SOMI/ GP[9]	M12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI, and GPIO. For GPIO, it is general-purpose input/output pin 9 (GP[9]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_D2/ McSPI_CS1/ GP[10]	K14	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI, and GPIO. For GPIO, it is general-purpose input/output pin 10 (GP[10]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
MMC1_D3/ McSPI_CS2/ GP[11]	L13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between MMC1, McSPI, and GPIO. For GPIO, it is general-purpose input/output pin 11 (GP[11]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1 (1C17h) register. The IPD is disabled at reset.
GP[12]/ UHPI_HD[2]	P7	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between GPIO and UHPI. For GPIO, it is general-purpose input/output pin 12 (GP[12]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[13]/ UHPI_HD[3]	N7	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between GPIO and UHPI. For GPIO, it is general-purpose input/output pin 13 (GP[13]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[14]/ UHPI_HD[4]	N8	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between GPIO and UHPI. For GPIO, it is general-purpose input/output pin 14 (GP[14]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[15]/ UHPI_HD[5]	P9	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between GPIO and UHPI. For GPIO, it is general-purpose input/output pin 15 (GP[15]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[16]/ UHPI_HD[6]	N9	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between GPIO and UHPI. For GPIO, it is general-purpose input/output pin 16 (GP[16]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[17]/ UHPI_HD[7]	P10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between GPIO and UHPI. For GPIO, it is general-purpose input/output pin 17 (GP[17]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
I2S2_CLK/ UHPI_HD[8]/ GP[18]/ SPI_CLK	N10	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO, and SPI. For GPIO, it is general-purpose input/output pin 18 (GP[18]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
I2S2_FS/ UHPI_HD[9]/ GP[19]/ SPI_CS0	P11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO and SPI. For GPIO, it is general-purpose input/output pin 19 (GP[19]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
I2S2_RX/ UHPI_HD[10]/ GP[20]/ SPI_RX	N11	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO and SPI. For GPIO, it is general-purpose input/output pin 20 (GP[20]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
GP[21]/ EM_A[15]	N1	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 21 (GP[21]). Mux control via the A15_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
GP[22]/ EM_A[16]	E2	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 22 (GP[22]). Mux control via the A16_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
GP[23]/ EM_A[17]	F2	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 23 (GP[23]). Mux control via the A17_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
GP[24]/ EM_A[18]	G2	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 24 (GP[24]). Mux control via the A18_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
GP[25]/ EM_A[19]	G4	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 25 (GP[25]). Mux control via the A19_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
GP[26]/ EM_A[20]	J3	I/O/Z	IPD DV_DDEMIF BH	This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 26 (GP[26]). Mux control via the A20_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2 (1C18h) register. The IPD is disabled at reset.
I2S2_DX/ UHPI_HD[11]/ GP[27]/ SPI_TX	P12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between I2S2, UHPI, GPIO, and SPI. For GPIO, it is general-purpose input/output pin 27 (GP[27]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.
UART_RTS/ UHPI_HD[12]/ GP[28]/ I2S3_CLK	N12	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. For GPIO, it is general-purpose input/output pin 28 (GP[28]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.
UART_CTS/ UHPI_HD[13]/ GP[29]/ I2S3_FS	P13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. For GPIO, it is general-purpose input/output pin 29 (GP[29]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
UART_RXD/ UHPI_HD[14]/ GP[30]/ I2S3_RX	N13	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. For GPIO, it is general-purpose input/output pin 30 (GP[30]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is enabled at reset.
UART_TXD/ UHPI_HD[15]/ GP[31]/ I2S3_DX	P14	I/O/Z	IPD DV_DDIO BH	This pin is multiplexed between UART, UHPI, GPIO, and I2S3. For GPIO, it is general-purpose input/output pin 31 (GP[31]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h) register. The IPD is disabled at reset.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

4.2.16 Regulators and Power Management

Table 4-17 Regulators and Power Management Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
Regulators
DSP_LDOO	E10	S		DSP_LDO output. When enabled, this output provides a regulated 1.3 V or 1.05 V output and up to 250 mA of current (see the I_SD parameter in Section 5.3.2, Electrical Characteristics). The DSP_LDO is intended to supply current to the digital core circuits only (CV_DD) but not to CV_DDRTC or external devices. For proper device operation, the external decoupling capacitor of this pin should be 5µF ~ 10µF. For more detailed information, see Section 5.7.2.5, Power-Supply Decoupling. When disabled, this pin is in the high-impedance (Hi-Z) state.
LDOI	F14, F13, B12	S		LDO inputs. For proper device operation, LDOI must always be powered. The LDOI pins must be connected to the same power supply source with a voltage range of 1.8 V to 3.6 V. These pins supply power to the internal LDOs, the bandgap reference generator circuits, and serve as the I/O supply for some input pins.
DSP_LDO_EN	D12	I	– LDOI	DSP_LDO enable input. This signal is not intended to be dynamically switched. 0 = DSP_LDO is enabled. The internal POR monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal. 1 = DSP_LDO is disabled. The internal POR voltage monitoring is also disabled. The internal POWERGOOD signal is forced high and the external reset signal on the RESET pin (D6) is the only source of the device reset. Note, the device's internal reset signal is generated as the logical AND of the RESET pin and the internal POWERGOOD signal.
USB_LDOO	F12	S		USB_LDO output. This output provides a regulated 1.3 V output and up to 25 mA of current (see the I_SD parameter in Section 5.3.2, Electrical Characteristics). For proper device operation, this pin must be connected to a 1 µF ~ 2 µF decoupling capacitor to V_SS. For more detailed information, see Section 5.7.2.5, Power-Supply Decoupling. This LDO is intended to supply power to the USB_V_DD1P3, USB_V_DDA1P3 pins but not to CV_DDRTC or external devices. Note: The reset state of the register that enables and disables the USB_LDO is dependent on the setting of CLK_SEL pin at reset. If CLK_SEL is high, the USB_LDO is disabled at reset but can be enabled by software. If CLK_SEL is low, the USB LDO is enabled (USB_LDO_EN=1) at reset and cannot be disabled by software. (See Section 5.7.2.1.1.2.1LDO Control for details.)
ANA_LDOO	A12	S		ANA_LDO output. This output provides a regulated 1.3 V output and up to 4 mA of current (see the I_SD parameter in Section 5.3.2, Electrical Characteristics). For proper device operation, this pin must be connected to an ~ 1.0 µF decoupling capacitor to V_SS. For more detailed information, see Section 5.7.2.5, Power-Supply Decoupling. This LDO is intended to supply power to the V_{DDA_ANA} pin but not to VDDA_PLL, CV_DDRTC or external devices.
BG_CAP	B13	A, O		Bandgap reference filter signal. For proper device operation, this pin needs to be bypassed with a 0.1 µF capacitor to analog ground (V_{SSA_ANA}). BG_CAP provides a settling time of 200 ms that must elapse before executing bootloader code. The settling time time is used by Timer0. This external capacitor provides filtering for stable reference voltages and currents generated by the bandgap circuit. The bandgap produces the references for use by the SAR and POR circuits.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

4.2.17 Supply Voltage

Table 4-18 Supply Voltage Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
SUPPLY VOLTAGES
	F6
	H8			1.05-V Digital Core supply voltage (75 MHz)
	J6	PWR		1.3-V Digital Core supply voltage (175 MHz)
CV_DD	K10			1.4-V Digital Core supply voltage (200 MHz)
	L5
	F7
	K7
DV_DDIO	K12	PWR		1.8-V, 2.75-V, or 3.3-V I/O power supply for non-EMIF and non-RTC I/Os
	N14			DV_DDIO must always be powered for proper operation.
	P3
	P8
	A2
	A5
	E6
	F5			1.8-V, 2.75-V, or 3.3-V EMIF I/O power supply
DV_DDEMIF	G5	PWR		DV_DDEMIF must always be powered for proper operation. GP[26:21] are used for boot mode configuration.
	H5
	H7
	J5
	P2
CV_DDRTC	C8	PWR		1.05-V RTC digital core and RTC oscillator power supply. Note: The CV_DDRTC pin must always be powered by an external power source even though RTC is not used. None of the on-chip LDOs can power CV_DDRTC.
DV_DDRTC	F8	PWR		1.8-V, 2.75-V, or 3.3-V I/O power supply for peripheral pins. DV_DDRTC can be tied to ground (V_SS) when RTC_CLKOUT and WAKEUP pins are not used permanently. In this case, the WAKEUP pin must be configured as output by software. (See Table 5-1, RTCPMGT Register Bit Descriptions.)
V_{DDA_PLL}	C10	PWR	see Section 5.2, ROC	1.3-V Analog PLL power supply for the system clock generator. Care should be taken to prevent noise on this supply. Consider using a ferrite bead if the power supply for this pin is shared with digital logic. See the Filtering Techniques Application Report [literature number: SCAA048] for more information. This signal cannot be powered from the ANA_LDOO pin. It must be powered externally.
USB_V_DDPLL	G8	S	see Section 5.2, ROC	3.3 V USB Analog PLL power supply. Care should be taken to prevent noise on this supply. Consider using a ferrite bead if the power supply for this pin is shared with digital logic. See the Filtering Techniques Application Report [literature number: SCAA048] for more information. When the USB peripheral is not used, the USB_V_DDPLL signal should be connected to ground (V_SS).
USB_V_DD1P3	J13	S	see Section 5.2, ROC	1.3-V digital core power supply for USB PHY. This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply Sequencing. When the USB peripheral is not used, the USB_V_DD1P3 signal should be connected to ground (V_SS).
USB_V_DDA1P3	H10	S	see Section 5.2, ROC	Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits] This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply Sequencing. When the USB peripheral is not used, the USB_V_DDA1P3 signal should be connected to ground (V_SS).
USB_V_DDA3P3	H12	S	see Section 5.2, ROC	Analog 3.3 V power supply for USB PHY. This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply Sequencing. When the USB peripheral is not used, the USB_V_DDA3P3 signal should be connected to ground (V_SS).
USB_V_DDOSC	G12	S	see Section 5.2, ROC	3.3-V power supply for USB oscillator. When the USB peripheral is not used, USB_V_DDOSC should be connected to ground (V_SS).
V_{DDA_ANA}	A10	PWR		1.3-V supply for power management and 10-bit SAR ADC This signal can be powered from the ANA_LDOO pin.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

4.2.18 Ground

Table 4-19 Ground Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
	A13
	A14
	D7
	D11
	E9
	E11
	E12
	E13
	E14
V_SS	F9	GND		Ground pins
	F10
	G6
	G7
	H6
	J7
	J8
	J9
	K8
	K9
	K11
	K13
V_SSRTC	C9	GND		Ground for RTC oscillator. When using a 32.768-kHz crystal, this pin is a local ground for the crystal and must not be connected to the board ground (See Figure 5-13 and Figure 5-16). When not using RTC and the crystal is not populated on the board, this pin is connected to the board ground.
V_{SSA_PLL}	D9	GND	see Section 5.2, ROC	Analog PLL ground for the system clock generator.
USB_V_SSPLL	G11	GND	see Section 5.2, ROC	USB Analog PLL ground.
USB_V_SS1P3	H13	GND	see Section 5.2, ROC	Digital core ground for USB PHY.
USB_V_SSA1P3	H9	GND	see Section 5.2, ROC	Analog ground for USB PHY [For high speed sensitive analog circuits].
USB_V_SSA3P3	H11	GND	see Section 5.2, ROC	Analog ground for USB PHY.
USB_V_SSOSC	F11	GND	see Section 5.2, ROC	Ground for USB oscillator.
USB_V_SSREF	G10	GND	see Section 5.2, ROC	Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to USB_R1. When the USB peripheral is not used, the USB_V_SSREF signal should be connected directly to ground (V_ss).
V_{SSA_ANA}	B10	GND		Analog ground pins for power management (POR and Bandgap circuits) and 10-bit SAR ADC
V_{SSA_ANA}	B14	GND

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal

4.3 Pin Multiplexing

Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. The external bus selection register (EBSR) controls all the pin multiplexing functions on the device.

This section discusses how to program the external bus selection register (EBSR) to select the desired peripheral functions and pin muxing. See the individual subsections for muxing details for a specific muxed pin. After changing any of the pin mux control registers, it will be necessary to reset the peripherals that are affected.

4.3.1 UHPI, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing [EBSR.PPMODE Bits]

The UHPI, SPI, UART, I2S2, I2S3, and GPIO signal muxing is determined by the value of the PPMODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 4-20.

Table 4-20 UHPI, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing

PULLUP and PULLDOWN CONTROL REGISTER BIT	PIN NUMBER	EBSR PPMODE BITS
		MODE 0	MODE 1	MODE 2	MODE 3	MODE 4	MODE 5	MODE 6
		000	001 (Reset Default)	010	011	100	101	110
PUDINHIBR7 (0x1C50) Bit 12	N3	UHPI_HINT	SPI_CLK	Reserved	Reserved	Reserved	Reserved	SPI_CLK
PUDINHIBR3 (0x1C19) Bit 0	P6	UHPI_HD[0]	SPI_RX	Reserved	Reserved	Reserved	Reserved	SPI_RX
PUDINHIBR3 (0x1C19) Bit 1	N6	UHPI_HD[1]	SPI_TX	Reserved	Reserved	Reserved	Reserved	SPI_TX
PUDINHIBR3 (0x1C19) Bit 2	P7	UHPI_HD[2]	GP[12]	Reserved	Reserved	Reserved	Reserved	GP[12]
PUDINHIBR3 (0x1C19) Bit 3	N7	UHPI_HD[3]	GP[13]	Reserved	Reserved	Reserved	Reserved	GP[13]
PUDINHIBR3 (0x1C19) Bit 4	N8	UHPI_HD[4]	GP[14]	Reserved	Reserved	Reserved	Reserved	GP[14]
PUDINHIBR3 (0x1C19) Bit 5	P9	UHPI_HD[5]	GP[15]	Reserved	Reserved	Reserved	Reserved	GP[15]
PUDINHIBR3 (0x1C19) Bit 6	N9	UHPI_HD[6]	GP[16]	Reserved	Reserved	Reserved	Reserved	GP[16]
PUDINHIBR3 (0x1C19) Bit 7	P10	UHPI_HD[7]	GP[17]	Reserved	Reserved	Reserved	Reserved	GP[17]
PUDINHIBR3 (0x1C19) Bit 8	N10	UHPI_HD[8]	I2S2_CLK	GP[18]	SPI_CLK	I2S2_CLK	SPI_CLK	I2S2_CLK
PUDINHIBR3 (0x1C19) Bit 9	P11	UHPI_HD[9]	I2S2_FS	GP[19]	SPI_CS0	I2S2_FS	SPI_CS0	I2S2_FS
PUDINHIBR3 (0x1C19) Bit 10	N11	UHPI_HD[10]	I2S2_RX	GP[20]	SPI_RX	I2S2_RX	SPI_RX	I2S2_RX
PUDINHIBR3 (0x1C19) Bit 11	P12	UHPI_HD[11]	I2S2_DX	GP[27]	SPI_TX	I2S2_DX	SPI_TX	I2S2_DX
PUDINHIBR3 (0x1C19) Bit 12	N12	UHPI_HD[12]	UART_RTS	GP[28]	I2S3_CLK	UART_RTS	UART_RTS	I2S3_CLK
PUDINHIBR3 (0x1C19) Bit 13	P13	UHPI_HD[13]	UART_CTS	GP[29]	I2S3_FS	UART_CTS	UART_CTS	I2S3_FS
PUDINHIBR3 (0x1C19) Bit 14	N13	UHPI_HD[14]	UART_RXD	GP[30]	I2S3_RX	UART_RXD	UART_RXD	I2S3_RX
PUDINHIBR3 (0x1C19) Bit 15	P14	UHPI_HD[15]	UART_TXD	GP[31]	I2S3_DX	UART_TXD	UART_TXD	I2S3_DX
PUDINHIBR7 (0x1C50) Bit 8	P4	UHPI_HCNTL0	SPI_CS0	Reserved	Reserved	Reserved	Reserved	SPI_CS0
PUDINHIBR7 (0x1C50) Bit 9	N4	UHPI_HCNTL1	SPI_CS1	Reserved	Reserved	Reserved	Reserved	SPI_CS1
PUDINHIBR7 (0x1C50) Bit 10	P5	UHPI_HR_NW	SPI_CS2	Reserved	Reserved	Reserved	Reserved	SPI_CS2
PUDINHIBR7 (0x1C50) Bit 11	N5	UHPI_HRDY	SPI_CS3	Reserved	Reserved	Reserved	Reserved	SPI_CS3
PUDINHIBR6 (0x1C4F) Bit 7	B5	UHPI_HBE0	EM_DQM0	EM_DQM0	EM_DQM0	EM_DQM0	EM_DQM0	EM_D1M0
PUDINHIBR6 (0x1C4F) Bit 8	P1	UHPI_HBE1	EM_DQM1	EM_DQM1	EM_DQM1	EM_DQM1	EM_DQM1	EM_DQM1
PUDINHIBR7 (0x1C50) Bit 3	A6	UHPI_HAS	EM_SDRAS	EM_SDRAS	EM_SDRAS	EM_SDRAS	EM_SDRAS	EM_SDRAS
PUDINHIBR7 (0x1C50) Bit 2	B4	UHPI_HCS	EM_SDCAS	EM_SDCAS	EM_SDCAS	EM_SDCAS	EM_SDCAS	EM_SDCAS
PUDINHIBR7 (0x1C50) Bit 4	B3	UHPI_HDS1	EM_CS0	EM_CS0	EM_CS0	EM_CS0	EM_CS0	EM_CS0
PUDINHIBR7 (0x1C50) Bit 5	A4	UHPI_HDS2	EM_CS1	EM_CS1	EM_CS1	EM_CS1	EM_CS1	EM_CS1
PUDINHIBR7 (0x1C50) Bit 1	N2	UHPI_HHWIL	EM_SDCKE	EM_SDCKE	EM_SDCKE	EM_SDCKE	EM_SDCKE	EM_SDCKE

4.3.2 MMC1, McSPI, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]

The MMC1, McSPI, and GPIO signal muxing is determined by the value of the SP1MODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 4-21.

Table 4-21 MMC1, McSPI, and GP[11:6] Pin Multiplexing

PUDINHIBR1 REGISTER BIT⁽¹⁾	PIN NUMBER	EBSR SP1MODE BITS
		MODE 0	MODE 1	MODE 2
		00 (Reset Default)	01	10
Bit 8	M13	MMC1_CLK	McSPI_CLK	GP[6]
Bit 9	L14	MMC1_CMD	McSPI_CS0	GP[7]
Bit 10	M14	MMC1_D0	McSPI_SIMO	GP[8]
Bit 11	M12	MMC1_D1	McSPI_SOMI	GP[9]
Bit 12	K14	MMC1_D2	McSPI_CS1	GP[10]
Bit 13	L13	MMC1_D3	McSPI_CS2	GP[11]

(1) The pin names with PUDINHIBR1 (1C17h) register bit field references can have the pulldown register enabled or disabled via this register. Pin 0 on serial port 1 corresponds to bit 8, pin 1 to bit 9, and so on up to pin 5 which corresponds to bit 13.

4.3.3 MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]

The MMC0, I2S0, McBSP, and GPIO signal muxing is determined by the value of the SP0MODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 4-22.

Table 4-22 MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing

PUDINHIBR1 REGISTER BIT⁽¹⁾	PIN NUMBER	EBSR SP0MODE BITS
		MODE 0	MODE 1	MODE 2	MODE 3
		00 (Reset Default)	01	10	11
Bit 0	L10	MMC0_CLK	I2S0_CLK	GP[0]	McBSP_CLKX
Bit 1	M11	MMC0_CMD	I2S0_FS	GP[1]	McBSP_FSX
Bit 2	L9	MMC0_D0	I2S0_DX	GP[2]	McBSP_DX
Bit 3	M10	MMC0_D1	I2S0_RX	GP[3]	McBSP_DR
Bit 4	L12	MMC0_D2	GP[4]	GP[4]	McBSP_FSR
Bit 5	L11	MMC0_D3	GP[5]	GP[5]	McBSP_CLKR_CLKS⁽²⁾

(1) The pin names with PUDINHIBR1 (1C17h) register bit field references can have the pulldown register enabled or disabled via this register. Pin 0 on serial port 0 corresponds to bit 0, pin 1 to bit 1, and so on up to pin 5 which corresponds to bit 5.

(2) Bit 15 of the EBSR register determines this port to be McBSP_CLKR or McBSP_CLKS.

4.3.4 EMIF EM_A[20:15] and GP[26:21] Pin Multiplexing [EBSR.Axx_MODE bits]

The EMIF Address and GPIO signal muxing is determined by the value of the A20_MODE, A19_MODE, A18_MODE, A17_MODE, A16_MODE, and A15_MODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 4-23.

Table 4-23 EM_A[20:16] and GP[26:21] Pin Multiplexing

PUDINHIBR2 REGISTER BIT⁽¹⁾	PIN NUMBER	Axx_MODE BIT
PUDINHIBR2 REGISTER BIT⁽¹⁾	PIN NUMBER	0	1
Bit 0	N1	EM_A[15]	GP[21]
Bit 1	E2	EM_A[16]	GP[22]
Bit 2	F2	EM_A[17]	GP[23]
Bit 3	G2	EM_A[18]	GP[24]
Bit 4	G4	EM_A[19]	GP[25]
Bit 5	J3	EM_A[20]	GP[26]

(1) The pin names with PUDINHIBR2 (1C18h) register bit field references can have the pulldown register enabled or disabled via this register.

4.4 Connections for Unused Signals

Table 4-24 lists the signals that are reserved or are not connected on this device.

Table 4-24 Reserved and No Connects Signal Descriptions

SIGNAL		TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾⁽⁴⁾	OTHER⁽²⁾⁽³⁾	DESCRIPTION
Reserved
RSV0	C12	I	– LDOI	Reserved. For proper device operation, this pin must be tied directly to V_SS.
RSV1	J10	PWR		Reserved. For proper device operation, this pin must be tied directly to CV_DD.
RSV2	J11	PWR		Reserved. For proper device operation, this pin must be tied directly to CV_DD.
RSV3	D14	I	– LDOI	Reserved. For proper device operation, this pin must be tied directly to V_SS.
RSV4	C14	I	– LDOI	Reserved. For proper device operation, this pin must be tied directly to V_SS.
RSV5	C13	I	– LDOI	Reserved. For proper device operation, this pin must be tied directly to V_SS.
RSV16	D13	I	– LDOI	Reserved. For proper device operation, this pin must be tied directly to V_SS.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(3) Specifies the operating I/O supply voltage for each signal