SPRS357D August   2006  – June 2020 TMS320F28044

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
      1. Table 5-1 TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      2. 5.4.1     Reducing Current Consumption
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for F28044 100-Ball GGM Package
    7. 5.7  Thermal Resistance Characteristics for F28044 100-Pin PZ Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-3 TMS320x280x Clock Table and Nomenclature
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-5 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-6 Input Clock Frequency
        2. Table 5-7 XCLKIN Timing Requirements - PLL Enabled
        3. Table 5-8 XCLKIN Timing Requirements - PLL Disabled
        4. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-10 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-11 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-12 IDLE Mode Timing Requirements
            2. Table 5-13 IDLE Mode Switching Characteristics
            3. Table 5-14 STANDBY Mode Timing Requirements
            4. Table 5-15 STANDBY Mode Switching Characteristics
            5. Table 5-16 HALT Mode Timing Requirements
            6. Table 5-17 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-18 ePWM Timing Requirements
            2. Table 5-19 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-20 Trip-Zone input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-21 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
          4. 5.9.4.2.4 ADC Start-of-Conversion Timing
            1. Table 5-22 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-23 External Interrupt Timing Requirements
          2. Table 5-24 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-25 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Master Mode Timing
          1. Table 5-26 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 5-27 SPI Master Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 SPI Slave Mode Timing
          1. Table 5-28 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 5-29 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 5.9.5 JTAG Debug Probe Connection Without Signal Buffering for the DSP
      6. 5.9.6 Flash Timing
        1. Table 5-30 Flash Endurance for A Temperature Material
        2. Table 5-31 Flash Parameters at 100-MHz SYSCLKOUT
        3. Table 5-32 Flash/OTP Access Timing
        4. Table 5-33 Flash Data Retention Duration
    10. 5.10 On-Chip Analog-to-Digital Converter
      1. Table 5-35 ADC Electrical Characteristics (over recommended operating conditions)
      2. 5.10.1     ADC Power-Up Control Bit Timing
        1. Table 5-36 ADC Power-Up Delays
        2. Table 5-37 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
      3. 5.10.2     Definitions
      4. 5.10.3     Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. Table 5-38 Sequential Sampling Mode Timing
      5. 5.10.4     Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. Table 5-39 Simultaneous Sampling Mode Timing
      6. 5.10.5     Detailed Descriptions
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  Flash
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0, L1 SARAMs
      8. 6.1.8  Boot ROM
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1, XINT2, XNMI)
      12. 6.1.12 Oscillator and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-Power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1 32-Bit CPU-Timers 0/1/2
      2. 6.2.2 Enhanced PWM Modules (ePWM1–16)
      3. 6.2.3 Hi-Resolution PWM (HRPWM)
      4. 6.2.4 Enhanced Analog-to-Digital Converter (ADC) Module
        1. 6.2.4.1 ADC Connections if the ADC Is Not Used
        2. 6.2.4.2 ADC Registers
      5. 6.2.5 Serial Communications Interface (SCI) Module (SCI-A)
      6. 6.2.6 Serial Peripheral Interface (SPI) Module (SPI-A)
      7. 6.2.7 Inter-Integrated Circuit (I2C)
      8. 6.2.8 GPIO MUX
    3. 6.3 Memory Map
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • PZ|100
サーマルパッド・メカニカル・データ
発注情報

6.2.2 Enhanced PWM Modules (ePWM1–16)

The F28044 device contains up to 16 enhanced PWM modules (ePWM). Figure 6-3 shows a block diagram of multiple ePWM modules. Figure 6-4 shows the signal interconnections with the ePWM. See the TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide for details.

TMS320F28044 pwm_prs357.gifFigure 6-3 Multiple PWM Modules

The F28044 device contains 16 enhanced PWM modules (ePWM) and 16 high resolution PWM modules (HRPWM). The ePWM modules synchronize input/output and the ADC start of conversion (SOCA/B) signals are regrouped in the F28044. At reset, EPWMMODE bits in the GPAMCFG register configure the sync signals to be compatible to the TMS320F2808 device. In F28044 mode, the ePWMMODE bits are set to 11 to select the EPWMA signals on all 16 GPIOs (GPIO0–GPIO15). This mode selection also reconfigures the EPWM1 SYNCOUT to be connected to four groups of ePWM modules and as EPWMSYNCO signals on the pin:

  • Group 1: ePWM2, ePWM3, ePWM4
  • Group 2: ePWM5, ePWM6, ePWM7, ePWM8
  • Group 3: ePWM9, ePWM10, ePWM11, ePWM12
  • Group 4: ePWM13, ePWM14, ePWM15, ePWM16

See the TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide for additional details.

Table 6-3 through Table 6-6 show the complete ePWM register set per module.

Table 6-3 ePWM1–4 Control and Status Registers

NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / #SHADOW DESCRIPTION
TBCTL 0x6800 0x6840 0x6880 0x68C0 1 / 0 Time Base Control Register
TBSTS 0x6801 0x6841 0x6881 0x68C1 1 / 0 Time Base Status Register
TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1 / 0 Time Base Phase HRPWM Register
TBPHS 0x6803 0x6843 0x6883 0x68C3 1 / 0 Time Base Phase Register
TBCTR 0x6804 0x6844 0x6884 0x68C4 1 / 0 Time Base Counter Register
TBPRD 0x6805 0x6845 0x6885 0x68C5 1 / 1 Time Base Period Register Set
CMPCTL 0x6807 0x6847 0x6887 0x68C7 1 / 0 Counter Compare Control Register
CMPAHR 0x6808 0x6848 0x6888 0x68C8 1 / 1 Time Base Compare A HRPWM Register
CMPA 0x6809 0x6849 0x6889 0x68C9 1 / 1 Counter Compare A Register Set
CMPB 0x680A 0x684A 0x688A 0x68CA 1 / 1 Counter Compare B Register Set
AQCTLA 0x680B 0x684B 0x688B 0x68CB 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x680F 0x684F 0x688F 0x68CF 1 / 1 Dead-Band Generator Control Register
DBRED 0x6810 0x6850 0x6890 0x68D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6811 0x6851 0x6891 0x68D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6812 0x6852 0x6892 0x68D2 1 / 0 Trip Zone Select Register(1)
TZCTL 0x6814 0x6854 0x6894 0x68D4 1 / 0 Trip Zone Control Register(1)
TZEINT 0x6815 0x6855 0x6895 0x68D5 1 / 0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6816 0x6856 0x6896 0x68D6 1 / 0 Trip Zone Flag Register
TZCLR 0x6817 0x6857 0x6897 0x68D7 1 / 0 Trip Zone Clear Register(1)
TZFRC 0x6818 0x6858 0x6898 0x68D8 1 / 0 Trip Zone Force Register(1)
ETSEL 0x6819 0x6859 0x6899 0x68D9 1 / 0 Event Trigger Selection Register
ETPS 0x681A 0x685A 0x689A 0x68DA 1 / 0 Event Trigger Prescale Register
ETFLG 0x681B 0x685B 0x689B 0x68DB 1 / 0 Event Trigger Flag Register
ETCLR 0x681C 0x685C 0x689C 0x68DC 1 / 0 Event Trigger Clear Register
ETFRC 0x681D 0x685D 0x689D 0x68DD 1 / 0 Event Trigger Force Register
PCCTL 0x681E 0x685E 0x689E 0x68DE 1 / 0 PWM Chopper Control Register
HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1 / 0 HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.

Table 6-4 ePWM5–8 Control and Status Registers

NAME ePWM5 ePWM6 ePWM7 ePWM8 SIZE (x16) / #SHADOW DESCRIPTION
TBCTL 0x6900 0x6940 0x6980 0x69C0 1 / 0 Time Base Control Register
TBSTS 0x6901 0x6941 0x6981 0x69C1 1 / 0 Time Base Status Register
TBPHSHR 0x6902 0x6942 0x6982 0x69C2 1 / 0 Time Base Phase HRPWM Register
TBPHS 0x6903 0x6943 0x6983 0x69C3 1 / 0 Time Base Phase Register
TBCTR 0x6904 0x6944 0x6984 0x69C4 1 / 0 Time Base Counter Register
TBPRD 0x6905 0x6945 0x6985 0x69C5 1 / 1 Time Base Period Register Set
CMPCTL 0x6907 0x6947 0x6987 0x69C7 1 / 0 Counter Compare Control Register
CMPAHR 0x6908 0x6948 0x6988 0x69C8 1 / 1 Time Base Compare A HRPWM Register
CMPA 0x6909 0x6949 0x6989 0x69C9 1 / 1 Counter Compare A Register Set
CMPB 0x690A 0x694A 0x698A 0x69CA 1 / 1 Counter Compare B Register Set
AQCTLA 0x690B 0x694B 0x698B 0x69CB 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x690C 0x694C 0x698C 0x69CC 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x690D 0x694D 0x698D 0x69CD 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x690E 0x694E 0x698E 0x69CE 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x690F 0x694F 0x698F 0x69CF 1 / 1 Dead-Band Generator Control Register
DBRED 0x6910 0x6950 0x6990 0x69D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6911 0x6951 0x6991 0x69D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6912 0x6952 0x6992 0x69D2 1 / 0 Trip Zone Select Register(1)
TZCTL 0x6914 0x6954 0x6994 0x69D4 1 / 0 Trip Zone Control Register(1)
TZEINT 0x6915 0x6955 0x6995 0x69D5 1 / 0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6916 0x6956 0x6996 0x69D6 1 / 0 Trip Zone Flag Register
TZCLR 0x6917 0x6957 0x6997 0x69D7 1 / 0 Trip Zone Clear Register(1)
TZFRC 0x6918 0x6958 0x6998 0x69D8 1 / 0 Trip Zone Force Register(1)
ETSEL 0x6919 0x6959 0x6999 0x69D9 1 / 0 Event Trigger Selection Register
ETPS 0x691A 0x695A 0x699A 0x69DA 1 / 0 Event Trigger Prescale Register
ETFLG 0x691B 0x695B 0x699B 0x69DB 1 / 0 Event Trigger Flag Register
ETCLR 0x691C 0x695C 0x699C 0x69DC 1 / 0 Event Trigger Clear Register
ETFRC 0x691D 0x695D 0x699D 0x69DD 1 / 0 Event Trigger Force Register
PCCTL 0x691E 0x695E 0x699E 0x69DE 1 / 0 PWM Chopper Control Register
HRCNFG 0x6920 0x6960 0x69A0 0x69E0 1 / 0 HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.

Table 6-5 ePWM9–12 Control and Status Registers

NAME ePWM9 ePWM10 ePWM11 ePWM12 SIZE (x16) / #SHADOW DESCRIPTION
TBCTL 0x6600 0x6640 0x6680 0x66C0 1 / 0 Time Base Control Register
TBSTS 0x6601 0x6641 0x6681 0x66C1 1 / 0 Time Base Status Register
TBPHSHR 0x6602 0x6642 0x6682 0x66C2 1 / 0 Time Base Phase HRPWM Register
TBPHS 0x6603 0x6643 0x6683 0x66C3 1 / 0 Time Base Phase Register
TBCTR 0x6604 0x6644 0x6684 0x66C4 1 / 0 Time Base Counter Register
TBPRD 0x6605 0x6645 0x6685 0x66C5 1 / 1 Time Base Period Register Set
CMPCTL 0x6607 0x6647 0x6687 0x66C7 1 / 0 Counter Compare Control Register
CMPAHR 0x6608 0x6648 0x6688 0x66C8 1 / 1 Time Base Compare A HRPWM Register
CMPA 0x6609 0x6649 0x6689 0x66C9 1 / 1 Counter Compare A Register Set
CMPB 0x660A 0x664A 0x668A 0x66CA 1 / 1 Counter Compare B Register Set
AQCTLA 0x660B 0x664B 0x668B 0x66CB 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x660C 0x664C 0x668C 0x66CC 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x660D 0x664D 0x668D 0x66CD 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x660E 0x664E 0x668E 0x66CE 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x660F 0x664F 0x668F 0x66CF 1 / 1 Dead-Band Generator Control Register
DBRED 0x6610 0x6650 0x6690 0x66D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6611 0x6651 0x6691 0x66D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6612 0x6652 0x6692 0x66D2 1 / 0 Trip Zone Select Register(1)
TZCTL 0x6614 0x6654 0x6694 0x66D4 1 / 0 Trip Zone Control Register(1)
TZEINT 0x6615 0x6655 0x6695 0x66D5 1 / 0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6616 0x6656 0x6696 0x66D6 1 / 0 Trip Zone Flag Register
TZCLR 0x6617 0x6657 0x6697 0x66D7 1 / 0 Trip Zone Clear Register(1)
TZFRC 0x6618 0x6658 0x6698 0x66D8 1 / 0 Trip Zone Force Register(1)
ETSEL 0x6619 0x6659 0x6699 0x66D9 1 / 0 Event Trigger Selection Register
ETPS 0x661A 0x665A 0x669A 0x66DA 1 / 0 Event Trigger Prescale Register
ETFLG 0x661B 0x665B 0x669B 0x66DB 1 / 0 Event Trigger Flag Register
ETCLR 0x661C 0x665C 0x669C 0x66DC 1 / 0 Event Trigger Clear Register
ETFRC 0x661D 0x665D 0x669D 0x66DD 1 / 0 Event Trigger Force Register
PCCTL 0x661E 0x665E 0x669E 0x66DE 1 / 0 PWM Chopper Control Register
HRCNFG 0x6620 0x6660 0x66A0 0x66E0 1 / 0 HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.

Table 6-6 ePWM13–16 Control and Status Registers

NAME ePWM13 ePWM14 ePWM15 ePWM16 SIZE (x16) / #SHADOW DESCRIPTION
TBCTL 0x6700 0x6740 0x6780 0x67C0 1 / 0 Time Base Control Register
TBSTS 0x6701 0x6741 0x6781 0x67C1 1 / 0 Time Base Status Register
TBPHSHR 0x6702 0x6742 0x6782 0x67C2 1 / 0 Time Base Phase HRPWM Register
TBPHS 0x6703 0x6743 0x6783 0x67C3 1 / 0 Time Base Phase Register
TBCTR 0x6704 0x6744 0x6784 0x67C4 1 / 0 Time Base Counter Register
TBPRD 0x6705 0x6745 0x6785 0x67C5 1 / 1 Time Base Period Register Set
CMPCTL 0x6707 0x6747 0x6787 0x67C7 1 / 0 Counter Compare Control Register
CMPAHR 0x6708 0x6748 0x6788 0x67C8 1 / 1 Time Base Compare A HRPWM Register
CMPA 0x6709 0x6749 0x6789 0x67C9 1 / 1 Counter Compare A Register Set
CMPB 0x670A 0x674A 0x678A 0x67CA 1 / 1 Counter Compare B Register Set
AQCTLA 0x670B 0x674B 0x678B 0x67CB 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x670C 0x674C 0x678C 0x67CC 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x670D 0x674D 0x678D 0x67CD 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x670E 0x674E 0x678E 0x67CE 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x670F 0x674F 0x678F 0x67CF 1 / 1 Dead-Band Generator Control Register
DBRED 0x6710 0x6750 0x6790 0x67D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6711 0x6751 0x6791 0x67D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6712 0x6752 0x6792 0x67D2 1 / 0 Trip Zone Select Register(1)
TZCTL 0x6714 0x6754 0x6794 0x67D4 1 / 0 Trip Zone Control Register(1)
TZEINT 0x6715 0x6755 0x6795 0x67D5 1 / 0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6716 0x6756 0x6796 0x67D6 1 / 0 Trip Zone Flag Register
TZCLR 0x6717 0x6757 0x6797 0x67D7 1 / 0 Trip Zone Clear Register(1)
TZFRC 0x6718 0x6758 0x6798 0x67D8 1 / 0 Trip Zone Force Register(1)
ETSEL 0x6719 0x6759 0x6799 0x67D9 1 / 0 Event Trigger Selection Register
ETPS 0x671A 0x675A 0x679A 0x67DA 1 / 0 Event Trigger Prescale Register
ETFLG 0x671B 0x675B 0x679B 0x67DB 1 / 0 Event Trigger Flag Register
ETCLR 0x671C 0x675C 0x679C 0x67DC 1 / 0 Event Trigger Clear Register
ETFRC 0x671D 0x675D 0x679D 0x67DD 1 / 0 Event Trigger Force Register
PCCTL 0x671E 0x675E 0x679E 0x67DE 1 / 0 PWM Chopper Control Register
HRCNFG 0x6720 0x6760 0x67A0 0x67E0 1 / 0 HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.
TMS320F28044 hires_prs357.gifFigure 6-4 ePWM Sub-Modules Showing Critical Internal Signal Interconnections