SPRS357D August   2006  – June 2020 TMS320F28044

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
      1. Table 5-1 TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      2. 5.4.1     Reducing Current Consumption
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for F28044 100-Ball GGM Package
    7. 5.7  Thermal Resistance Characteristics for F28044 100-Pin PZ Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-3 TMS320x280x Clock Table and Nomenclature
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-5 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-6 Input Clock Frequency
        2. Table 5-7 XCLKIN Timing Requirements - PLL Enabled
        3. Table 5-8 XCLKIN Timing Requirements - PLL Disabled
        4. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-10 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-11 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-12 IDLE Mode Timing Requirements
            2. Table 5-13 IDLE Mode Switching Characteristics
            3. Table 5-14 STANDBY Mode Timing Requirements
            4. Table 5-15 STANDBY Mode Switching Characteristics
            5. Table 5-16 HALT Mode Timing Requirements
            6. Table 5-17 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-18 ePWM Timing Requirements
            2. Table 5-19 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-20 Trip-Zone input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-21 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
          4. 5.9.4.2.4 ADC Start-of-Conversion Timing
            1. Table 5-22 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-23 External Interrupt Timing Requirements
          2. Table 5-24 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-25 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Master Mode Timing
          1. Table 5-26 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 5-27 SPI Master Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 SPI Slave Mode Timing
          1. Table 5-28 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 5-29 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 5.9.5 JTAG Debug Probe Connection Without Signal Buffering for the DSP
      6. 5.9.6 Flash Timing
        1. Table 5-30 Flash Endurance for A Temperature Material
        2. Table 5-31 Flash Parameters at 100-MHz SYSCLKOUT
        3. Table 5-32 Flash/OTP Access Timing
        4. Table 5-33 Flash Data Retention Duration
    10. 5.10 On-Chip Analog-to-Digital Converter
      1. Table 5-35 ADC Electrical Characteristics (over recommended operating conditions)
      2. 5.10.1     ADC Power-Up Control Bit Timing
        1. Table 5-36 ADC Power-Up Delays
        2. Table 5-37 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
      3. 5.10.2     Definitions
      4. 5.10.3     Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. Table 5-38 Sequential Sampling Mode Timing
      5. 5.10.4     Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. Table 5-39 Simultaneous Sampling Mode Timing
      6. 5.10.5     Detailed Descriptions
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  Flash
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0, L1 SARAMs
      8. 6.1.8  Boot ROM
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1, XINT2, XNMI)
      12. 6.1.12 Oscillator and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-Power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1 32-Bit CPU-Timers 0/1/2
      2. 6.2.2 Enhanced PWM Modules (ePWM1–16)
      3. 6.2.3 Hi-Resolution PWM (HRPWM)
      4. 6.2.4 Enhanced Analog-to-Digital Converter (ADC) Module
        1. 6.2.4.1 ADC Connections if the ADC Is Not Used
        2. 6.2.4.2 ADC Registers
      5. 6.2.5 Serial Communications Interface (SCI) Module (SCI-A)
      6. 6.2.6 Serial Peripheral Interface (SPI) Module (SPI-A)
      7. 6.2.7 Inter-Integrated Circuit (I2C)
      8. 6.2.8 GPIO MUX
    3. 6.3 Memory Map
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

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発注情報

6.4 Register Map

The F28044 device contains three peripheral register spaces. The spaces are categorized as follows:

Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 6-16.
Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 6-17.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 6-18.

Table 6-16 Peripheral Frame 0 Registers(1)(2)

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE(3)
Device Emulation Registers 0x0880 – 0x09FF 384 EALLOW protected
FLASH Registers(4) 0x0A80 – 0x0ADF 96 EALLOW protected
CSM Protected
Code Security Module Registers 0x0AE0 – 0x0AEF 16 EALLOW protected
ADC Result Registers (dual-mapped) 0x0B00 – 0xB0F 16 Not EALLOW protected
CPU-TIMER0/1/2 Registers 0x0C00 – 0x0C3F 64
PIE Registers 0x0CE0 – 0x0CFF 32
PIE Vector Table 0x0D00 – 0x0DFF 256 EALLOW protected
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) Missing segments of memory space are reserved and should not be used in applications.
(3) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents.
(4) The Flash Registers are also protected by the Code Security Module (CSM).

Table 6-17 Peripheral Frame 1 Registers(1)(2)

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
ePWM1 + HRPWM Registers 0x6800 – 0x683F 64 Some ePWM registers are EALLOW protected. See Table 6-3 through Table 6-6.
ePWM2 + HRPWM Registers 0x6840 – 0x687F 64
ePWM3 + HRPWM Registers 0x6880 – 0x68BF 64
ePWM4 + HRPWM Registers 0x68C0 – 0x68FF 64
ePWM5 + HRPWM Registers 0x6900 – 0x693F 64
ePWM6 + HRPWM Registers 0x6940 – 0x697F 64
ePWM7 + HRPWM Registers 0x6980 – 0x69BF 64
ePWM8 + HRPWM Registers 0x69C0 – 0x69FF 64
ePWM9 + HRPWM Registers 0x6600 – 0x663F 64
ePWM10 + HRPWM Registers 0x6640 – 0x667F 64
ePWM11 + HRPWM Registers 0x6680 – 0x66BF 64
ePWM12 + HRPWM Registers 0x66C0 – 0x66FF 64
ePWM13 + HRPWM Registers 0x6700 – 0x673F 64
ePWM14 + HRPWM Registers 0x6740 – 0x677F 64
ePWM15 + HRPWM Registers 0x6780 – 0x67BF 64
ePWM16 + HRPWM Registers 0x67C0 – 0x67FF 64
GPIO Control Registers 0x6F80 – 0x6FBF 128 EALLOW protected
GPIO Data Registers 0x6FC0 – 0x6FDF 32 Not EALLOW protected
GPIO Interrupt and LPM Select Registers 0x6FE0 – 0x6FFF 32 EALLOW protected
(1) All 32-bit accesses are aligned to even address boundaries.
(2) Missing segments of memory space are reserved and should not be used in applications.

Table 6-18 Peripheral Frame 2 Registers(1)(2)

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
System Control Registers 0x7010 – 0x702F 32 EALLOW Protected
SPI-A Registers 0x7040 – 0x704F 16 Not EALLOW Protected
SCI-A Registers 0x7050 – 0x705F 16
External Interrupt Registers 0x7070 – 0x707F 16
ADC Registers 0x7100 – 0x711F 32
I2C Registers 0x7900 – 0x792F 48
(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
(2) Missing segments of memory space are reserved and should not be used in applications.