JAJSEZ7H October   2014  – March 2020 TMS320F28075 , TMS320F28076

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pins With Internal Pullup and Pulldown
    4. 4.4 Pin Multiplexing
      1. 4.4.1 GPIO Muxed Pins
      2. 4.4.2 Input X-BAR
      3. 4.4.3 Output X-BAR and ePWM X-BAR
      4. 4.4.4 USB Pin Muxing
      5. 4.4.5 High-Speed SPI Pin Muxing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 Device Current Consumption at 120-MHz SYSCLK
      2. Table 5-2 Device Current Consumption at 120-MHz SYSCLK With the Internal VREG Enabled
      3. 5.5.1     Current Consumption Graphs
      4. 5.5.2     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PTP Package
      2. 5.7.2 PZP Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  System
      1. 5.9.1 Power Management
        1. 5.9.1.1 Internal 1.2-V VREG
        2. 5.9.1.2 Power Sequencing
          1. 5.9.1.2.1 Signal Pin Requirements
          2. 5.9.1.2.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements
          3. 5.9.1.2.3 VDD Requirements
          4. 5.9.1.2.4 Supply Ramp Rate
            1. Table 5-4 Supply Ramp Rate
          5. 5.9.1.2.5 Supply Supervision
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Sources
        2. 5.9.2.2 Reset Electrical Data and Timing
          1. Table 5-5 Reset (XRS) Timing Requirements
          2. Table 5-6 Reset (XRS) Switching Characteristics
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1 Clock Sources
        2. 5.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-8  Input Clock Frequency
            2. Table 5-9  X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
            3. Table 5-10 X1 Timing Requirements
            4. Table 5-11 AUXCLKIN Timing Requirements
            5. Table 5-12 PLL Lock Times
          2. 5.9.3.2.2 Internal Clock Frequencies
            1. Table 5-13 Internal Clock Frequencies
          3. 5.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 5-14 Output Clock Frequency
            2. Table 5-15 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 5.9.3.3 Input Clocks and PLLs
        4. 5.9.3.4 Crystal Oscillator
          1. Table 5-16 Crystal Oscillator Parameters
          2. Table 5-18 Crystal Oscillator Electrical Characteristics
        5. 5.9.3.5 Internal Oscillators
          1. Table 5-19 Internal Oscillator Electrical Characteristics
      4. 5.9.4 Flash Parameters
        1. Table 5-21 Flash Parameters
      5. 5.9.5 Emulation/JTAG
        1. 5.9.5.1 JTAG Electrical Data and Timing
          1. Table 5-22 JTAG Timing Requirements
          2. Table 5-23 JTAG Switching Characteristics
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO - Output Timing
          1. Table 5-24 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO - Input Timing
          1. Table 5-25 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
      7. 5.9.7 Interrupts
        1. 5.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-26 External Interrupt Timing Requirements
          2. Table 5-27 External Interrupt Switching Characteristics
      8. 5.9.8 Low-Power Modes
        1. 5.9.8.1 Clock-Gating Low-Power Modes
        2. 5.9.8.2 Power-Gating Low-Power Modes
        3. 5.9.8.3 Low-Power Mode Wakeup Timing
          1. Table 5-30 IDLE Mode Timing Requirements
          2. Table 5-31 IDLE Mode Switching Characteristics
          3. Table 5-32 STANDBY Mode Timing Requirements
          4. Table 5-33 STANDBY Mode Switching Characteristics
          5. Table 5-34 HALT Mode Timing Requirements
          6. Table 5-35 HALT Mode Switching Characteristics
          7. Table 5-36 HIBERNATE Mode Timing Requirements
          8. Table 5-37 HIBERNATE Mode Switching Characteristics
      9. 5.9.9 External Memory Interface (EMIF)
        1. 5.9.9.1 Asynchronous Memory Support
        2. 5.9.9.2 Synchronous DRAM Support
        3. 5.9.9.3 EMIF Electrical Data and Timing
          1. 5.9.9.3.1 Asynchronous RAM
            1. Table 5-38 EMIF Asynchronous Memory Timing Requirements
            2. Table 5-39 EMIF Asynchronous Memory Switching Characteristics
          2. 5.9.9.3.2 Synchronous RAM
            1. Table 5-40 EMIF Synchronous Memory Timing Requirements
            2. Table 5-41 EMIF Synchronous Memory Switching Characteristics
    10. 5.10 Analog Peripherals
      1. 5.10.1 Analog-to-Digital Converter (ADC)
        1. 5.10.1.1 ADC Configurability
          1. 5.10.1.1.1 Signal Mode
        2. 5.10.1.2 ADC Electrical Data and Timing
          1. Table 5-43 ADC Operating Conditions
          2. Table 5-44 ADC Characteristics
          3. Table 5-45 ADCEXTSOC Timing Requirements
          4. 5.10.1.2.1 ADC Input Model
            1. Table 5-46 Single-Ended Input Model Parameters
          5. 5.10.1.2.2 ADC Timing Diagrams
            1. Table 5-49 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
        3. 5.10.1.3 Temperature Sensor Electrical Data and Timing
          1. Table 5-50 Temperature Sensor Electrical Characteristics
      2. 5.10.2 Comparator Subsystem (CMPSS)
        1. 5.10.2.1 CMPSS Electrical Data and Timing
          1. Table 5-51 Comparator Electrical Characteristics
          2. Table 5-52 CMPSS DAC Static Electrical Characteristics
      3. 5.10.3 Buffered Digital-to-Analog Converter (DAC)
        1. 5.10.3.1 Buffered DAC Electrical Data and Timing
          1. Table 5-53 Buffered DAC Electrical Characteristics
    11. 5.11 Control Peripherals
      1. 5.11.1 Enhanced Capture (eCAP)
        1. 5.11.1.1 eCAP Electrical Data and Timing
          1. Table 5-54 eCAP Timing Requirement
          2. Table 5-55 eCAP Switching Characteristics
      2. 5.11.2 Enhanced Pulse Width Modulator (ePWM)
        1. 5.11.2.1 Control Peripherals Synchronization
        2. 5.11.2.2 ePWM Electrical Data and Timing
          1. Table 5-56 ePWM Timing Requirements
          2. Table 5-57 ePWM Switching Characteristics
          3. 5.11.2.2.1 Trip-Zone Input Timing
            1. Table 5-58 Trip-Zone Input Timing Requirements
        3. 5.11.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-59 External ADC Start-of-Conversion Switching Characteristics
      3. 5.11.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.11.3.1 eQEP Electrical Data and Timing
          1. Table 5-60 eQEP Timing Requirements
          2. Table 5-61 eQEP Switching Characteristics
      4. 5.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.11.4.1 HRPWM Electrical Data and Timing
          1. Table 5-62 High-Resolution PWM Timing Requirements
          2. Table 5-63 High-Resolution PWM Characteristics
      5. 5.11.5 Sigma-Delta Filter Module (SDFM)
        1. 5.11.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. Table 5-64 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 5.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)
          1. Table 5-65 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option
    12. 5.12 Communications Peripherals
      1. 5.12.1 Controller Area Network (CAN)
      2. 5.12.2 Inter-Integrated Circuit (I2C)
        1. 5.12.2.1 I2C Electrical Data and Timing
          1. Table 5-66 I2C Timing Requirements
          2. Table 5-67 I2C Switching Characteristics
      3. 5.12.3 Multichannel Buffered Serial Port (McBSP)
        1. 5.12.3.1 McBSP Electrical Data and Timing
          1. 5.12.3.1.1 McBSP Transmit and Receive Timing
            1. Table 5-68 McBSP Timing Requirements
            2. Table 5-69 McBSP Switching Characteristics
          2. 5.12.3.1.2 McBSP as SPI Master or Slave Timing
            1. Table 5-70 McBSP as SPI Master Timing Requirements
            2. Table 5-71 McBSP as SPI Master Switching Characteristics
            3. Table 5-72 McBSP as SPI Slave Timing Requirements
            4. Table 5-73 McBSP as SPI Slave Switching Characteristics
      4. 5.12.4 Serial Communications Interface (SCI)
      5. 5.12.5 Serial Peripheral Interface (SPI)
        1. 5.12.5.1 SPI Electrical Data and Timing
          1. 5.12.5.1.1 SPI Master Mode Timings
            1. Table 5-74 SPI Master Mode Timing Requirements
            2. Table 5-75 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. Table 5-76 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          2. 5.12.5.1.2 SPI Slave Mode Timings
            1. Table 5-77 SPI Slave Mode Timing Requirements
            2. Table 5-78 SPI Slave Mode Switching Characteristics
      6. 5.12.6 Universal Serial Bus (USB) Controller
        1. 5.12.6.1 USB Electrical Data and Timing
          1. Table 5-79 USB Input Ports DP and DM Timing Requirements
          2. Table 5-80 USB Output Ports DP and DM Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Memory
      1. 6.3.1 C28x Memory Map
      2. 6.3.2 Flash Memory Map
      3. 6.3.3 EMIF Chip Select Memory Map
      4. 6.3.4 Peripheral Registers Memory Map
      5. 6.3.5 Memory Types
        1. 6.3.5.1 Dedicated RAM (Mx and Dx RAM)
        2. 6.3.5.2 Local Shared RAM (LSx RAM)
        3. 6.3.5.3 Global Shared RAM (GSx RAM)
        4. 6.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 6.4  Identification
    5. 6.5  Bus Architecture – Peripheral Connectivity
    6. 6.6  C28x Processor
      1. 6.6.1 Floating-Point Unit
      2. 6.6.2 Trigonometric Math Unit
    7. 6.7  Control Law Accelerator
    8. 6.8  Direct Memory Access
    9. 6.9  Boot ROM and Peripheral Booting
      1. 6.9.1 EMU Boot or Emulation Boot
      2. 6.9.2 WAIT Boot Mode
      3. 6.9.3 Get Mode
      4. 6.9.4 Peripheral Pins Used by Bootloaders
    10. 6.10 Dual Code Security Module
    11. 6.11 Timers
    12. 6.12 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
    13. 6.13 Watchdog
    14. 6.14 Configurable Logic Block (CLB)
    15. 6.15 Functional Safety
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 デバイスおよび開発ツールの項目表記
    2. 8.2 マーキング
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Support Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PZP|100
  • PTP|176
サーマルパッド・メカニカル・データ
発注情報