JAJSHM4U April   2001  – July 2019 TMS320F2810 , TMS320F2811 , TMS320F2812

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
      2. 5.5.1     Current Consumption Graphs
      3. 5.5.2     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics for 179-Ball ZHH Package
    8. 5.8  Thermal Resistance Characteristics for 179-Ball GHH Package
    9. 5.9  Thermal Resistance Characteristics for 176-Pin PGF Package
    10. 5.10 Thermal Resistance Characteristics for 128-Pin PBK Package
    11. 5.11 Thermal Design Considerations
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1 Timing Parameter Symbology
        1. 5.12.1.1 General Notes on Timing Parameters
        2. 5.12.1.2 Test Load Circuit
        3. 5.12.1.3 Signal Transition Levels
      2. 5.12.2 Power Supply Sequencing
      3. 5.12.3 Reset Timing
        1. Table 5-3 Reset (XRS) Timing Requirements
      4. 5.12.4 Clock Specifications
        1. 5.12.4.1 Device Clock Table
          1. Table 5-4 Clock Table and Nomenclature
        2. 5.12.4.2 Clock Requirements and Characteristics
          1. 5.12.4.2.1 Input Clock Requirements
            1. Table 5-5 Input Clock Frequency
            2. Table 5-6 XCLKIN Timing Requirements – PLL Bypassed or Enabled
            3. Table 5-7 XCLKIN Timing Requirements – PLL Disabled
          2. 5.12.4.2.2 Output Clock Characteristics
            1. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      5. 5.12.5 Peripherals
        1. 5.12.5.1  General-Purpose Input/Output (GPIO) – Output Timing
          1. Table 5-10 General-Purpose Output Switching Characteristics
        2. 5.12.5.2  General-Purpose Input/Output (GPIO) – Input Timing
          1. Table 5-11 General-Purpose Input Timing Requirements
        3. 5.12.5.3  Event Manager Interface
          1. 5.12.5.3.1 PWM Timing
            1. Table 5-12 PWM Switching Characteristics
            2. Table 5-13 Timer and Capture Unit Timing Requirements
            3. Table 5-14 External ADC Start-of-Conversion – EVA – Switching Characteristics
            4. Table 5-15 External ADC Start-of-Conversion – EVB – Switching Characteristics
        4. 5.12.5.4  Low-Power Mode Wakeup Timing
          1. Table 5-16 IDLE Mode Timing Requirements
          2. Table 5-17 IDLE Mode Switching Characteristics
          3. Table 5-18 STANDBY Mode Timing Requirements
          4. Table 5-19 STANDBY Mode Switching Characteristics
          5. Table 5-20 HALT Mode Timing Requirements
          6. Table 5-21 HALT Mode Switching Characteristics
        5. 5.12.5.5  Serial Peripheral Interface (SPI) Master Mode Timing
          1. Table 5-22 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 5-23 SPI Master Mode External Timing (Clock Phase = 1)
        6. 5.12.5.6  Serial Peripheral Interface (SPI) Slave Mode Timing
          1. Table 5-24 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 5-25 SPI Slave Mode External Timing (Clock Phase = 1)
        7. 5.12.5.7  External Interface (XINTF) Timing
          1. 5.12.5.7.1 USEREADY = 0
          2. 5.12.5.7.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
          3. 5.12.5.7.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        8. 5.12.5.8  XINTF Signal Alignment to XCLKOUT
        9. 5.12.5.9  External Interface Read Timing
          1. Table 5-28 External Memory Interface Read Switching Characteristics
          2. Table 5-29 External Memory Interface Read Timing Requirements
        10. 5.12.5.10 External Interface Write Timing
          1. Table 5-30 External Memory Interface Write Switching Characteristics
        11. 5.12.5.11 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-31 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
          2. Table 5-32 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
          3. Table 5-33 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
          4. Table 5-34 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
        12. 5.12.5.12 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-35 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
          2. Table 5-36 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
          3. Table 5-37 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
        13. 5.12.5.13 XHOLD and XHOLDA
        14. 5.12.5.14 XHOLD/XHOLDA Timing
          1. Table 5-38 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
          2. Table 5-39 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
        15. 5.12.5.15 On-Chip Analog-to-Digital Converter
          1. Table 5-40  ADC Absolute Maximum Ratings Over Recommended Operating Conditions (Unless Otherwise Noted)
          2. Table 5-41  ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—AC Specifications
          3. Table 5-42  ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—DC Specifications
          4. 5.12.5.15.1 Current Consumption for Different ADC Configurations
            1. Table 5-43 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
          5. 5.12.5.15.2 ADC Power-Up Control Bit Timing
            1. Table 5-44 ADC Power-Up Delays
          6. 5.12.5.15.3 Detailed Description
            1. 5.12.5.15.3.1 Reference Voltage
            2. 5.12.5.15.3.2 Analog Inputs
            3. 5.12.5.15.3.3 Converter
            4. 5.12.5.15.3.4 Conversion Modes
          7. 5.12.5.15.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
            1. Table 5-45 Sequential Sampling Mode Timing
          8. 5.12.5.15.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
            1. Table 5-46 Simultaneous Sampling Mode Timing
          9. 5.12.5.15.6 Definitions of Specifications and Terminology
        16. 5.12.5.16 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.12.5.16.1 McBSP Transmit and Receive Timing
            1. Table 5-47 McBSP Timing Requirements
            2. Table 5-48 McBSP Switching Characteristics
          2. 5.12.5.16.2 McBSP as SPI Master or Slave Timing
            1. Table 5-49 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-50 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-51 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-52 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-53 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-54 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-55 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-56 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      6. 5.12.6 Emulator Connection Without Signal Buffering for the DSP
      7. 5.12.7 Interrupt Timing
        1. Table 5-57 Interrupt Switching Characteristics
        2. Table 5-58 Interrupt Timing Requirements
      8. 5.12.8 Flash Timing
        1. Table 5-59 Flash Endurance for A and S Temperature Material
        2. Table 5-60 Flash Endurance for Q Temperature Material
        3. Table 5-61 Flash Parameters at 150-MHz SYSCLKOUT
        4. Table 5-62 Flash/OTP Access Timing
        5. Table 5-63 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1  Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF) (F2812 Only)
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0, L1, H0 SARAMs
      9. 6.1.9  Boot ROM
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1, XINT2, XINT13, XNMI)
      13. 6.1.13 Oscillator and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-Power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2  Peripherals
      1. 6.2.1 32-Bit CPU-Timers 0/1/2
      2. 6.2.2 Event Manager Modules (EVA, EVB)
        1. 6.2.2.1 General-Purpose (GP) Timers
        2. 6.2.2.2 Full-Compare Units
        3. 6.2.2.3 Programmable Deadband Generator
        4. 6.2.2.4 PWM Waveform Generation
        5. 6.2.2.5 Double Update PWM Mode
        6. 6.2.2.6 PWM Characteristics
        7. 6.2.2.7 Capture Unit
        8. 6.2.2.8 Quadrature-Encoder Pulse (QEP) Circuit
        9. 6.2.2.9 External ADC Start-of-Conversion
      3. 6.2.3 Enhanced Analog-to-Digital Converter (ADC) Module
      4. 6.2.4 Enhanced Controller Area Network (eCAN) Module
      5. 6.2.5 Multichannel Buffered Serial Port (McBSP) Module
      6. 6.2.6 Serial Communications Interface (SCI) Module
      7. 6.2.7 Serial Peripheral Interface (SPI) Module
      8. 6.2.8 GPIO MUX
    3. 6.3  Memory Maps
    4. 6.4  Register Map
    5. 6.5  Device Emulation Registers
    6. 6.6  External Interface, XINTF (F2812 Only)
      1. 6.6.1 Timing Registers
      2. 6.6.2 XREVISION Register
    7. 6.7  Interrupts
      1. 6.7.1 External Interrupts
    8. 6.8  System Control
    9. 6.9  OSC and PLL Block
      1. 6.9.1 Loss of Input Clock
    10. 6.10 PLL-Based Clock Module
    11. 6.11 External Reference Oscillator Clock Option
    12. 6.12 Watchdog Block
    13. 6.13 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスおよび開発ツールの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PBK|128
サーマルパッド・メカニカル・データ
発注情報

6.2.1 32-Bit CPU-Timers 0/1/2

There are three 32-bit CPU-timers on the F281x devices (CPU-TIMER0/1/2).

Timer 2 is reserved for DSP/BIOS. CPU-Timer 0 and CPU-Timer 1 can be used in user applications. These timers are different from the general-purpose (GP) timers that are present in the Event Manager modules (EVA, EVB).

NOTE

If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application.
TMS320F2810 TMS320F2811 TMS320F2812 cputim_prs174.gifFigure 6-1 CPU-Timers

In the F281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 6-2.

TMS320F2810 TMS320F2811 TMS320F2812 intsig_prs174.gif
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 6-2 CPU-Timer Interrupts Signals and Output Signal

The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value in the period register “PRDH:PRD”. The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 6-3 are used to configure the timers. For more information, see the TMS320x281x DSP System Control and Interrupts Reference Guide.

Table 6-3 CPU-Timers 0, 1, 2 Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION
TIMER0TIM 0x00 0C00 1 CPU-Timer 0, Counter Register
TIMER0TIMH 0x00 0C01 1 CPU-Timer 0, Counter Register High
TIMER0PRD 0x00 0C02 1 CPU-Timer 0, Period Register
TIMER0PRDH 0x00 0C03 1 CPU-Timer 0, Period Register High
TIMER0TCR 0x00 0C04 1 CPU-Timer 0, Control Register
Reserved 0x00 0C05 1
TIMER0TPR 0x00 0C06 1 CPU-Timer 0, Prescale Register
TIMER0TPRH 0x00 0C07 1 CPU-Timer 0, Prescale Register High
TIMER1TIM 0x00 0C08 1 CPU-Timer 1, Counter Register
TIMER1TIMH 0x00 0C09 1 CPU-Timer 1, Counter Register High
TIMER1PRD 0x00 0C0A 1 CPU-Timer 1, Period Register
TIMER1PRDH 0x00 0C0B 1 CPU-Timer 1, Period Register High
TIMER1TCR 0x00 0C0C 1 CPU-Timer 1, Control Register
Reserved 0x00 0C0D 1
TIMER1TPR 0x00 0C0E 1 CPU-Timer 1, Prescale Register
TIMER1TPRH 0x00 0C0F 1 CPU-Timer 1, Prescale Register High
TIMER2TIM 0x00 0C10 1 CPU-Timer 2, Counter Register
TIMER2TIMH 0x00 0C11 1 CPU-Timer 2, Counter Register High
TIMER2PRD 0x00 0C12 1 CPU-Timer 2, Period Register
TIMER2PRDH 0x00 0C13 1 CPU-Timer 2, Period Register High
TIMER2TCR 0x00 0C14 1 CPU-Timer 2, Control Register
Reserved 0x00 0C15 1
TIMER2TPR 0x00 0C16 1 CPU-Timer 2, Prescale Register
TIMER2TPRH 0x00 0C17 1 CPU-Timer 2, Prescale Register High
Reserved 0x00 0C18 – 0x00 0C3F 40