JAJSFY0C August   2018  – December 2018 TMUX1208 , TMUX1209

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      アプリケーションの例
      2.      TMUX1208、TMUX1209のブロック図
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions TMUX1208
    2.     Pin Functions TMUX1209
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics (VDD = 5 V ±10 %)
    6. 7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
    7. 7.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
    8. 7.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1  On-Resistance
      2. 8.1.2  Off-Leakage Current
      3. 8.1.3  On-Leakage Current
      4. 8.1.4  Transition Time
      5. 8.1.5  Break-Before-Make
      6. 8.1.6  tON(EN) and tOFF(EN)
      7. 8.1.7  Charge Injection
      8. 8.1.8  Off Isolation
      9. 8.1.9  Crosstalk
      10. 8.1.10 Bandwidth
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail to Rail Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
      5. 8.3.5 Device Functional Modes
      6. 8.3.6 Truth Tables
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
    5. 9.5 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Information
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Fail-Safe Logic

The TMUX1208 and TMUX1209 have Fail-Safe Logic on the control input pins (EN, A0. A1, A2) allowing for operation up to 5.5 V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic feature allows the select pins of the TMUX1208 or TMUX1209 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature enables operation of the multiplexers with VDD = 1.2 V while allowing the select pins to interface with a logic level of another device up to 5.5 V.