SLLSE38B June 2010 – March 2016 TPD8E003
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPD8E003 offers eight ESD clamp circuits in a space-saving DQD package. When placed near the connector, the TPD8E003 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD8E003 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike.
For this design example, one TPD8E003 is used to protect an 8-pin GPIO header.
Given the example application, the parameters listed in Table 1 are known.
|Signal Range on Protected Lines||0 V to 5 V|
|Required Level of IEC ESD Protection||±8kV Contact, ±15kV Air Gap|
To begin the design process, some parameters must be decided upon; the designer must know the following:
The TPD8E003 supports signal ranges between 0 V and 5.5 V, which supports the GPIO application.
The TPD8E003 is rated to withstand up to ±12-kV contact and ±15-kV air gap IEC ESD. This meets the IEC ESD design target with room to spare.