9.1.1 Voltage Monitoring

Power faults are reported in the UVLOMon register. Each UVLOMon bit initializes to 0 upon a cold power up. After a fault is detected, the appropriate fault bit is latched high. Writing to the RST_ERRFLG (REG77) clears all UVLOMon bits. Table 39 summarizes the power device faults and actions.

9.1.2 Spindle Motor Driver Operating Sequence

When the VSPM is set to a positive DAC code, it enters into acceleration mode. Initial position sense (IS) mode then operates, as the start-up circuits offer the start-up pattern sequence to the driver, then switch to spin-up mode by detecting the rotor position using the BEMF signal from the spindle motor coil.

The spin-down and brake function are also controlled by the DAC value VSPM. When it has set the brake command to the VSPM, the driver goes into active-brake mode, then switches to short-brake mode in slow revolution speed, and then stops automatically. EXOR of a three-phase signal comprises the FG signal and is output from the XFG pin as shown in Figure 49.

Figure 49. Spindle Operating Sequence

Use the down-edge of the FG signal for monitoring FG frequency.

Short brake mode asserts after 300 ms if the FG signal stays L-level in deceleration.

This value is the nominal number of using a 12-poles motor.

The internal circuit starts 800 µs (typical) after the RDY pin changes to 'H'.　Recommended marginal delay value is 1 ms.

9.1.3 Auto Short Brake Function

The TPIC2050 provides an auto short brake function that selects a brake mode automatically by motor speed. Auto short brake includes two modes: short brake and active brake. If a value of 0xF90 or less is set to the VSPM, the brake mode automatically changes at rotation speed. This function enables low-power consumption and silent braking. Figure 50 shows the relation between brake mode and speed. The over-speed protect function suspends the SPM driver output at 15000 or more revolutions.

Each threshold value has hysteresis.
Brake mode will change to specific mode at the threshold speed after it reaches a speed about 15% higher than a threshold speed.

NOTE:

These speed values are the nominal number of using a 12-pole motor. In applying to a 16-pole motor, the rotation speed becomes 75% of indicated rpm values.

Figure 50. Brake Mode Selection

9.1.4 Spindle PWM Control

The output PWM duty of the spindle is controlled by the DAC code (VSPM). The gain in acceleration setting is always 14 times, but the maximum output is restricted to P12V voltage. A dead band with an output = 0 exists in the width between ±0x52 focusing on zero.

Figure 51. Spindle PWM Control

9.1.5 Spindle Driver Current Limiting Circuit

The current limit circuit monitors the RCS voltage at the ICOM pin and limits the output current by reducing the PWM duty when detecting overcurrent conditions.

9.1.6 Sled Driver Part

The sled driver outputs the PWM pulse set as DAC code (VSLDx) with current feedback. The maximum output is restricted to 880 mA at 0x7FF and 0x800. A dead band with an output = 0 exists in the width of ±0x33 focusing on zero.

Figure 52. Sled Output Current

Both outputs of SLED1/2 are 'H' when the input code is in the dead band.

9.1.7 Stepping Driver Part

The step driver outputs the PWM pulse, set as an 8-bit DAC code (VSTPx) using VSTP[11:4]. There is no feedback monitor for output. The pulse width is output according to the P5V power supply voltage.

Figure 53. Step Output Duty

9.1.8 Focus/Track/Tilt Driver Part

Figure 54. FCS/TRK/TLT Output Duty

9.1.9 Load Driver Part

The load driver outputs the voltage with the voltage feedback corresponding to the input DAC value. This channel has power voltage compensation, and is thus suited for slot-in type load control. This channel becomes active exclusively to other actuator channels. The load driver is shared with the TRK driver.

Figure 55. Load Output Duty

9.1.10 End Detect Function

This device has end position detection for the sled and collimator lens. This function eliminates the position switch at the PUH inner and collimator lens end positions. This function is enabled by ENDDET_ENA = 1, setting the object actuator (ENDDET_SEL = 00: for sled / ENDDET_SEL = 01: for step). When this function is enabled, internal logic detects the sled out zero-cross point, then the internal BEMF detect circuit measures the BEMF level of the stepping motor. There are four threshold levels. If the BEMF is lower than the selected threshold, the device recognizes the motor at stop and sets the ENDDET bit to 1. The ENDDET bit is then cleared at the BEMF voltage exceed threshold.

Figure 56. Timing of Sled End Detection

For the purpose of getting the correct stepping motor BEMF, choose a control frequency higher than 110 Hz (440 pps). This control frequency depends on the stepping motor characteristics.

Figure 57. Timing of Step End Detection

The recommended control speed is around 1200 pps for getting the correct BEMF level. This depends on the stepping motor characteristic. Evaluate your condition appropriately.

9.1.11 Load Tray Lock Detect Function

The tray lock detect function detects an inserted obstacle when the tray opens and closes, using the load motor BEMF. Adjusting TRAY_LOCKDET [2:0] (REG75) by the characteristic of a motor is required for an optimal threshold level. The designer can set a threshold level from 100 to 400 mA, with a 50-mA step, using TRAY_LOCKDET.

Observe the lock detection by reading the ENDDET (REG7F) flag where ENDDET_SEL = 2 or 3 is set.

Figure 58. Load Tray Lock Detect

9.1.12 Three-Beam Laser Diode Driver

The device has a circuit for the three-beam laser diode drivers containing Blu-ray™. The output is chosen with LDD_MSEL (REG71), and the LD drive current is outputted by input 11-bit DAC code to VLDD[10:0] and VLDDIN with analog input. The change in analog mode and digital mode is set up by LDD_AMODE (REG74). The MSB of VLDD is the sign bit and is ignored if it set to 1. All output, including BD, DVD, and CD, has an internal pulldown 3 kΩ.

The mode change delay circuit and LVP are integrated to prevent a rush of current when the mode changes. When the LDD mode is changed, VLDD<10:0> is cleared to 0 to prevent the selected laser diode from breaking, as LDD sets the current value according to each kind.

Figure 59. VLDD vs Output Average Current

9.1.13 Monitor Signal on GPOUT

The device can output a specific signal to the GPOUT pin. To output a signal, choose a signal from REG6F by enabling it first, then enabling GPOUT_ENA. When two or more signals are set for GPOUT, the output is a logical sum.

9.1.14 Example Timing of Target Control System

The TPIC2050 is designed to meet the requirements for updating control data in 400 kHz. Table 42 lists examples of the control system parameters. It takes 0.51 µs to transmit a 16-bit data packet to the TPIC2050 with a 35-MHz SCLK. Therefore, DSP can be sent in four packets at a 400-kHz interval. If the SCLK is lower than 28.8 MHz, the user must reduce the packet quantity to less than three. For example, the Focus/Truck command updates every 2.5 µs (400 kHz), and is able to send another two kinds of packets in this same slot. Figure 60 shows an example of the control timing when using the TPIC2050.

Figure 60. Example DAC Control

9.2.1 Design Requirements

To begin the design process, determine the following:

1. Motor configuration: The user can use all motor channels or part of them.
2. Usage for ILDD: BD, DVD, or CD
3. RDY pin can be connected to Host CPU, then Host CPU can know the power supply status of TPIC2050.

9.2.2 Detailed Design Procedure

After power up on 5-V and 12-V supply, register can be changed following way and enabling motors.

1. Set WRITE_ENABLE = 1 on REG76 via SPI.
2. Set XSLEEP = 1 at REG70
3. Enable motor channel by ENA_XXX bits on REG70
4. Change the DAC settings for the motor on REG01-0B. Then, output channels start driving load.

9.2.3 Application Curves

Figure 62. TRK Driver: DAC Code vs Output On Duty

Figure 63. Load Driver: DAC Code vs Output On Duty