SLIS167 Data sheet

SLIS167 August 2015 TPIC2050

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

DFD|56
- MPDS375

サーマルパッド・メカニカル・データ

DFD|56
- PPTD164E

発注情報

8 Detailed Description

8.1 Overview

TPIC2050 is very-low noise type motor driver IC suitable for 12V ODD. The 9-channels driver IC controlled by serial I/F is optimum for driving a spindle motor, a sled motor (stepping motor applicable), a load motor, and Focus / Tracking / Tilt actuators and stepping motor for collimator lens. This IC’s integrated current sense resistance which measures SPM current then it is able to reduce drive system cost in drastically. The spindle motor driver part builds in the sensor less logic which attained low noise-operation at the time of starting and run. In order to carry out self-starting by the starting circuit and to perform position detection by BEMF of a motor, sensors, such as a Hall device, are not needed. As the output stage of all channels works in efficient PWM driving, it is possible to attain low power operation by PWM control. Dead zone less control is possible for a Focus / Tracking / Tilt actuator driver. In addition, the spindle part output current limiting circuit, the thermal shut down circuit, the sled end detection circuit, collimator lens end detection circuit, actuator protection.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Protect Functions

The TPIC2050 has five protection features to protect target equipment: overvoltage protection (OVP), short-circuit protection (SCP), overcurrent protection (OCP), thermal protection (TSD), and actuator temperature protection (ACTTIMER).

8.3.1.1 OVP

OVP function protects the unit from the supplying high voltage. When the supply voltage exceeds 6.2 V (for P5V), all driver output goes to Hi-Z. The SPM, sled, and load channels go to Hi-Z when P12V is over 14.9 V. When power supply exceeds 14.1 V, the SPM channel enters short brake mode. This operation occurs after a rise in voltage in the motor BEMF. Regardless of the input voltage of the P5V12L, the load channel becomes Hi-Z when OVP_P5V or OVP_P12V. When the supply voltage falls below 6 V, all outputs start to operate again (14.6 V for 12-V driver channel). The OVP and POR (RDY) functions do not interlock. This function is intended to protect the device in the evaluation stage as a temporary and back-up solution.

8.3.1.2 OCP and SCP

The OCP and SCP protect the device from a breakdown caused by a large current. The OCP is provided only for the step channel, and SCP is provided for all driver channels other than the LDD driver. Table 1 indicates each behavior.

Table 1. Protection Threshold Table

BLOCK	FUNCTION	DETECTION CURRENT	DETECT TIME	HI-Z HOLD TIME
STEP driver	OCP	850 mA	1 µs	25 ms
STEP driver (low-side FET only)	SCP	Monitor driver output voltage High-side FET output V = GND Low-side FET output V = Supply V	0.8 to 1.6 µs	1.6 ms
SPM driver
Sled driver
Load driver
Actuator driver

When a large current is detected on each block, the device puts the output FET to Hi-Z.

When OCP or SCP occurs, it returns automatically after the set Hi-Z hold time expires. The OCPSCPERR (REG7F) and OCP, SCP flags (REG7B) are set at detection.

8.3.1.2.1 OCP for Step Driver

The STP1 and STP2 channels have current trip function. The output of the STEP channel is changed to Hi-Z if the current exceeds the current limit threshold (850 mA typical). When the trip period (25 ms) expires, the trip state is automatically released.

TPIC2050 slis167_over_curr_prot_step.gif

Figure 6. Overcurrent Protection Step

8.3.1.2.2 SCP

The SCP function monitors the output voltage of the high-side and low-side FET of the output driver, and when the setting voltage is not outputted, it recognizes it as 'SCP' and changes the output to Hi-Z. It automatically returns to the original state after 1.6 ms.

Figure 7. Example of SCP (Driver Short to GND)

8.3.1.3 Thermal Protection (TSD)

The TSD is a protection function which intercepts an output and suspends an operation when the IC temperature exceeds a maximum permissible safe temperature. TSD creates an output Hi-Z when the temperature rises up and a threshold value is exceeded. The two levels for the threshold are alert and trip. An alarm is given by status register TSD_FAULT_ on Alert level at 135°C. If the temperature continues to rise, the register TSD_ is set at 150°C and the driver output changes to Hi-Z. If the temperature falls and reaches 135°C, it outputs again. The TPIC2050 has 11 temperature sensors in each circuit block. The particular sensor assigned to the appropriate status flag is listed in Table 2.

Table 2. Thermal Sensor Assignment

CIRCUIT	ALERT (°C)	TRIP (°C)	RELEASE (°C)	ALERT FLAG	TRIP FLAG
U	135	150	135	TSD_FAULT_SPM	TSD_SPM
V	135	150	135	TSD_FAULT_SPM	TSD_SPM
W	135	150	135	TSD_FAULT_SPM	TSD_SPM
TLT	135	150	135	TSD_FAULT_ACT	TSD_ACT
FCS	135	150	135	TSD_FAULT_ACT	TSD_ACT
TRK	135	150	135	TSD_FAULT_ACT	TSD_ACT
SLED1	135	150	135	TSD_FAULT_ACT	TSD_ACT
SLED2	135	150	135	TSD_FAULT_ACT	TSD_ACT
STP	135	150	135	TSD_FAULT_ACT	TSD_ACT
LOAD	135	150	135	TSD_FAULT_ACT	TSD_ACT
LDD	135	150	135	TSD_FAULT_LDD	TSD_LDD

8.3.1.4 Actuator Temperature Protection (ACTTIMER)

The TPIC2050 has an actuator protect function, ACTTIMER. This function sets the actuator channel output to Hi-Z when the actuator coil current exceeds a specific value. This new protection calculates heat accumulation and judges appropriately. When this function operates, the LDD and load driver channel outputs are Hi-Z, and the spindle channel is forced to auto short brake, stopping the disc motor.

The user can know if protection occurred by checking the Fault register ACTTIMER_FAULT (REG7F) and ACT_TIMER_PROT (REG78). ACTTIMER_FAULT sets a character of advance notice, before detecting ACT_TIMER_PROT. After an ACT_TIMER_PROT is set, even if the temperature falls, it does not automatically release protection. The user must clear the flag by setting the RST_ERR_FLAG (REG77) or setting 0 to ACTTEMPTH (REG72). The ACTTIMER function is disabled by setting H to ACTPROT_OFF (REG72) or setting 0 to ACTTEMPTH (REG72). To acquire the optimal value for ACTTEMPTH, set the device into the condition of the detection level and read the value of ACTTEMP, as the present value can be read from ACTTEMP (REG78). The ACTTEMP data is updated on the register in ACTPROT_OFF = 0 and ACTTEMPTH > 0.

Figure 8. Actuator Temperature Protections

8.3.1.5 Prevent OVP 12 V (PREOVP-12V)

When using the power supply unit without current-sinking capability for 12-V supply, the P12V voltage goes up with the motor BEMF at slowdown. As a result, 12-V OVP is detected if this voltage exceeds the threshold value. To prevent this detection, the TPIC2050 provides a PREOVP-12V function. The SPM driver output is forced into three-phase short brake mode if P12V is over the threshold voltage. The PREOVP-12V function is disabled by OVPPRE12V_OFF = 1 (REG6B[0]).

Figure 9. OVPPRE_12V

8.3.2 DAC Type

The TPIC2050 has nine channel drivers and one LDD driver. Each channel is assigned to the most suitable DAC engine with a different type. ACT (focus/tracking/tilt) has a 12-bit DAC. Upper 8 (MSB sign bit) are converted one at a time in 5 MHz, and LSB 4 bits are output in sequence with a 1.25 MHz PWM. SPIN and Load DAC have the same types and sampling rate of 312 kHz. The SPM channel has x14 gain, and other channels (except for SLED and STP) have x6 gain. The DAC for STP is 8-bits resolution output with 40-kHz PWM, and no feedback. The gain for STP is x5 relative to P5V voltage. Table 3 shows the configuration of each driver.

Table 3. DAC Type

	FCS/TRK/TLT	SLED	SPIN	LOAD	STP	LDD
Resolution	12 bit	10 bit	12 bit	12 bit	8 bit	11 bit
Type	8-bit oversampling	10-bit voltage DAC	8-bit over sampling	8-bit over sampling	1-bit direct duty PWM	11-bit voltage DAC
Sampling	1.25M / 10 bit 312K / 12 bit		312K	312K	40 kHz
PWM frequency	312 kHz	About 156 kHz (variable)	156 kHz	312 kHz	40 kHz
Out range	±6 V	±880 mA	±14 V	±6 V	±(P5V*1)	0 to 120 mA
Feedback	Voltage F/B	Current F/B	Power supply compensation	Voltage F/B shared with TRK	Direct PWM no F/B	No F/B

8.3.3 Example of 12-Bit DAC Sampling Rate for FCS/TRK/TLT

The input data is separated in the upper 8 bits and the lower 4 bits. Upper 8 bits (MSB sign 1 bit) are put into an 8-bit current DAC in every 5 MHz. The lower 4 bits are put into one bit current DAC in sequence, from the upper to lower bit. This is a one bit DAC output with PWM in 1.25 MHz. At any PWM duty, 100%, 75%, 50%, 25% or 0% is summed in 8-bit current DAC every 1.25 MHz. Therefore, it takes 3.2 µs for all lower 4 bits to sum to the PWM output. As a result, 12-bit data is sampled in every PWM cycle. An example of the sampling rate for FCS/TRK/TLT is in Figure 10.

TPIC2050 slis167_ex_12_bit_dac_cov_time.gif

Figure 10. Example of 12-Bit DAC Conversion Time (FCS/TRK/TLT)

8.3.4 Digital Input Coding

The output voltage (current) is commanded via programming to the DAC. All of the DAC input format is 12 bit in complement of 2's, though some DAC has a low resolution. When 12 bits data is inputted as 8-bits DAC, the TPIC2050 recognizes four subordinate position bits (LSB) as 0. To arrange for 12-bit DAC format, the DSP should shift 8-bit or 10-bit data to an appropriate bit position. The full scale is ±1.0 V, and the driver gain is set to 6 or 14. The output voltage (V_out) is given by the following equation:

Equation 1. TPIC2050 slis167_eq1.gif

where

bit[11:0] is the digital input value, range 000000000000b to 111111111111b

Table 4. DAC Format

^MSB DIGITAL INPUT (BIN) ^LSB	HEX	DEC	VDAC	ANALOG OUTPUT (5 V)	ANALOG OUTPUT (12 V)
1000_0000_0000	0x800	–2048	–0.9995	–5.997	–13.993
1000_0000_0001	0x801	–2047	–0.9995	–5.997	–13.993
1111_1111_1111	0xFFF	–1	–0.0005	–0.003	–0.007
0000_0000_0000	0x000	0	0	0.000	0.000
0000_0000_0001	0x001	1	0.0005	0.003	0.007
0111_1111_1110	0x7FE	2046	0.9990	5.994	13.986
0111_1111_1111	0x7FF	2047	0.9995	5.997	13.993

TPIC2050 slis167_output_volt_vs_dac_code.gif

Figure 11. Output Voltage vs DAC Code

8.4 Device Functional Modes

8.4.1 Differential Tilt Mode

The TPIC2050 supports differential tilt mode, which outputs the value calculated from focus and tilt. Focus and tilt can be set in differential mode by DIFF_TLT (REG74) = 1. Because focus and tilt are updated at the same time, the update interval of tilt can be thinned out. Output data changes after writing the VFCS data; therefore, write VFCS data when setting VTLT. In differential mode, the output value is calculated as follows:

Equation 2. FCS_OUT = (VFCS + VTLT) × 6

Equation 3. TLT_OUT = (VFCS – VTLT) × 6

8.4.2 Power-On Reset (POR)

8.4.2.1 RDY (Power Ready)

The TPIC2050 prepares the RDY pin to show a power status to the host controller. A device sets RDY output to high (= POR) if the supply voltage and internal regulator voltage reach a rated value. All registers initialize at the time of the POR operation. Figure 12 shows the behavior of RDY.

Figure 12. RDY Pin Behavior

8.5 Programming

8.5.1 Serial Port Functional Description

The serial communication of the TPIC2050 is based on an SPI communications protocol. The TPIC2050 is put on the slave side. All 16-bit transmission data is effective in SSZ = L period.

The bit stream sent through SIMO from a master (DSP) is latched to an internal shift register by the rising edge of SCLK. All the data is transmitted in a 16-bit command and data format. A format has two types of data, 8 bits and 12 bits in length. To access specific registers, an address and R/W flag are specified as a command part. In addition, 12-bit data does not have an R/W flag in the packet, because the DAC registers　(= 12-bit data form) are Write only. A transfer packet (command and data) is transmitted sequentially from MSB to LSB. A packet is distinguished in MSB by 2 bits of command. In the case of 11, it handles a packet for control register access, and the other is processed as a packet for a DAC data setting.

The four kinds of serial-data communication packets are:

Write 12 bits DAC data (MSB two bit ≠ 11)
Write 8 bits control register (MSB two bit = 11)
Read 8 bits control register (MSB two bit = 11)
Write 12 bits focus DAC data + Read 8 bits status register at the same time (MSB two bit ≠ 11)

8.5.2 Write Operation

For write operations, the DSP transmits 16-bit (command + address + data) data in order from MSB. Only the 16-bit data, which means 16 SCLK sent from the master during SSZ = L, becomes effective. If more than 17 or less than 15 SCLK pulses are received during the time that SSZ is low, the whole packet is ignored. For all valid write operations, the data of the shift register is latched into its designated internal register at the rising edge of the 16^th SCLK. All internal register bits, except indicated otherwise, are reset to their default states upon power-on reset.

TPIC2050 slis167_write_12_bits_dac_data.gif

Figure 13. Write 12-Bits DAC Data

TPIC2050 slis167_write_8_bits_ctrl_reg.gif

Figure 14. Write 8-Bits Control Register

8.5.3 Read Operation

The DSP sends an 8-bit header through SIMO to perform a Read operation. The TPIC2050 starts to drive the SOMI line upon the eighth falling edge of SCLK and shifts out eight data bits. The master DSP inputs 8-bit data from SOMI after the ninth rising edge of SCLK. 　

TPIC2050 slis167_read_8_bits_ctrl_reg.gif

Figure 15. Read 8-Bits Control Register

8.5.4 Write and Read Operation

Optionally, the master DSP can read the Status register while writing the 12 bits DAC (Focus DAC) packet. This is enabled by setting the bit RDSTAT_ON_VFCS (REG74) = H.

TPIC2050 slis167_wr_12_bits_focus_read_8_bits.gif

Figure 16. Write 12-Bits Focus DAC Data + Read 8-Bits Status Data

8.6 Register Maps

All registers are in WRITE-protect mode after XRSTIN release. WRITE_ENA bit (REG76) = 1 is required before writing data in the register.

8.6.1 Register State Transition

Figure 17. Register Behavior

8.6.2 DAC Register (12-Bit Write Only)

Two different forms apply to the 12-bit DAC registers. The forms can be selected by setting VDAC_MAPSW (REG74h).

Table 5. DAC Register (VDAC_MAPSW = 0)

Reg	Name	11	10	9	8	7	6	5	4	3	2	1	0
00h	N/A	N/A
01h	VTLT	VTLT [11]	VTLT [10]	VTLT [9]	VTLT [8]	VTLT [7]	VTLT[6]	VTLT[5]	VTLT[4]	VTLT[3]	VTLT[2]	VTLT[1]	VTLT[0]
02h	VFCS	VFCS [11]	VFCS [10]	VFCS [9]	VFCS [8]	VFCS [7]	VFCS[6]	VFCS[5]	VFCS[4]	VFCS[3]	VFCS[2]	VFCS[1]	VFCS[0]
03h	VTRK	VTRK [11]	VTRK [10]	VTRK [9]	VTRK [8]	VTRK [7]	VTRK[6]	VTRK[5]	VTRK[4]	VTRK[3]	VTRK[2]	VTRK[1]	VTRK[0]
04h	VSLD1	VSLD1 [11]	VSLD1 [10]	VSLD1 [9]	VSLD1 [8]	VSLD1 [7]	VSLD1 [6]	VSLD1 [5]	VSLD1 [4]	VSLD1[3]	VSLD1[2]	VSLD1[1]⁽¹⁾	VSLD1[0]⁽¹⁾
05h	VSLD2	VSLD2 [11]	VSLD2 [10]	VSLD2 [9]	VSLD2 [8]	VSLD2 [7]	VSLD2 [6]	VSLD2 [5]	VSLD2 [4]	VSLD2[3]	VSLD2[2]	VSLD2[1]⁽¹⁾	VSLD2[0]⁽¹⁾
06h	VSTP1	VSTP1 [11]	VSTP1 [10]	VSTP1 [9]	VSTP1 [8]	VSTP1 [7]	VSTP1 [6]	VSTP1 [5]	VSTP1 [4]	VSTP1[3]⁽¹⁾	VSTP1[2]⁽¹⁾	VSTP1[1]⁽¹⁾	VSTP1[0]⁽¹⁾
07h	VSTP2	VSTP2 [11]	VSTP2 [10]	VSTP2 [9]	VSTP2 [8]	VSTP2 [7]	VSTP2 [6]	VSTP2 [5]	VSTP2 [4]	VSTP2[3]⁽¹⁾	VSTP2[2]⁽¹⁾	VSTP2[1]⁽¹⁾	VSTP2[0]⁽¹⁾
08h	VSPM	VSPM [11]	VSPM [10]	VSPM [9]	VSPM [8]	VSPM [7]	VSPM[6]	VSPM[5]	VSPM[4]	VSPM[3]	VSPM[2]	VSPM[1]	VSPM[0]
09h	VLOAD	VLOAD [11]	VLOAD [10]	VLOAD [9]	VLOAD [8]	VLOAD [7]	VLOAD [6]	VLOAD [5]	VLOAD [4]	VLOAD[3]	VLOAD[2]	VLOAD[1]	VLOAD[0]
0Ah	VLDD	VLDD [11]	VLDD [10]	VLDD [9]	VLDD [8]	VLDD [7]	VLDD[6]	VLDD[5]	VLDD[4]	VLDD[3]	VLDD[2]	VLDD[1]	VLDD[0]
0Bh	N/A	N/A

(1) TPIC2050 processes as 0 even if set to 1

Table 6. DAC Register (VDAC_MAPSW = 1)

Reg	Name	11	10	9	8	7	6	5	4	3	2	1	0
00h	N/A	N/A
01h	VTRK	VTRK [11]	VTRK [10]	VTRK[9]	VTRK[8]	VTRK[7]	VTRK[6]	VTRK[5]	VTRK[4]	VTRK[3]	VTRK[2]	VTRK[1]	VTRK[0]
02h	VFCS	VFCS [11]	VFCS [10]	VFCS[9]	VFCS[8]	VFCS[7]	VFCS[6]	VFCS[5]	VFCS[4]	VFCS[3]	VFCS[2]	VFCS[1]	VFCS[0]
03h	VTLT	VTLT [11]	VTLT [10]	VTLT[9]	VTLT[8]	VTLT[7]	VTLT[6]	VTLT[5]	VTLT[4]	VTLT[3]	VTLT[2]	VTLT[1]	VTLT[0]
04h	VSLD1	VSLD1 [11]	VSLD1 [10]	VSLD1 [9]	VSLD1 [8]	VSLD1 [7]	VSLD1 [6]	VSLD1 [5]	VSLD1 [4]	VSLD1 [3]	VSLD1 [2]	VSLD1 [1]⁽¹⁾	VSLD1 [0]⁽¹⁾
05h	VSLD2	VSLD2 [11]	VSLD2 [10]	VSLD2 [9]	VSLD2 [8]	VSLD2 [7]	VSLD2 [6]	VSLD2 [5]	VSLD2 [4]	VSLD2 [3]	VSLD2 [2]	VSLD2 [1]⁽¹⁾	VSLD2 [0]⁽¹⁾
06h	VSPM	VSPM [11]	VSPM [10]	VSPM[9]	VSPM[8]	VSPM[7]	VSPM[6]	VSPM[5]	VSPM[4]	VSPM[3]	VSPM[2]	VSPM[1]	VSPM[0]
07h	VLDD	VLDD [11]	VLDD [10]	VLDD[9]	VLDD[8]	VLDD[7]	VLDD[6]	VLDD[5]	VLDD[4]	VLDD[3]	VLDD[2]	VLDD[1]	VLDD[0]
08h	N/A	N/A
09h	VLOAD	N/A				VLOAD [11]	VLOAD [10]	VLOAD [9]	VLOAD [8]	VLOAD [7]	VLOAD [6]	VLOAD [5]	VLOAD [4]
0Ah	VSTP1	N/A				VSTP1 [11]	VSTP1 [10]	VSTP1 [9]	VSTP1 [8]	VSTP1 [7]	VSTP1 [6]	VSTP1 [5]	VSTP1 [4]
0Bh	VSTP2	N/A				VSTP2 [11]	VSTP2 [10]	VSTP2 [9]	VSTP2 [8]	VSTP2 [7]	VSTP2 [6]	VSTP2 [5]	VSTP2 [4]

(1) TPIC2050 processes as 0 even if set to 1

8.6.3 Control Register (8-Bit Read/Write)

Table 7. Control Register (8-Bit Read/Write)

Reg	Name	F	7	6	5	4	3	2	1	0
70h	DriverEna	R/W	TLT_ENA	FCS_ENA	TRK_ENA	SPM_ENA	SLD_ENA	STP_ENA	LOAD_ENA	XSLEEP
71h	FuncEna	R/W	TI Rsvd	ENDDET _ENA	ENDDET_SEL		LDD_ENA	LDD_MSEL		TEMPMON _ENA
72h	ACTCfg	R/W	P12VMUTE _NORST	RSTIN_OFF	ACTPROT _OFF	ACTTEMPTH
73h	Parm0	R/W	SIF_TIMEOUT_TH		SLEDEND _HZTIME	SLDENDTH		STPEND _HZTIME	STPENDTH
74h	SIFCfg	R/W	DIFF_TLT	LDD_AMODE	STATUS _ON_VFCS	VSLD2 _POL	VSTP2 _POL	ADVANCE _RD	SOMI_HIZ	VDAC _MAPSW
75h	Parm1	R/W	TRAY_LOCKDET			TI Reserved		SPM_FAST_BRK	SPM_SLNT_BRK	SPM _HIZMODE
76h	WriteEna	R/W	WRITE _ENABLE	TI Reserved						REG6X _Write
77h	ClrReg	W	RST_INDAC	RST_REGS	RST_ERR _FLAG	TI Reserved
78h	ActTemp	R	TI Reserved		ACT_TIMER _PROT	ACTTEMP
79h	UVLOMon	R	TI Reserved		UVLO_P5V	UVLO _INT3P3	UVLO _P12V	UVLO_SIOV	OVP_P5V	OVP_P12V
7Ah	TSDMon	R	TI Rsvd	TSD _FAULT _SPM	TSD _FAULT _ACT	TSD _FAULT _LDD	TI Rsvd	TSD_SPM	TSD_ACT	TSD _LDD
7Bh	OCPMon	R	TI Reserved		OCP_STP	SCP_SPM	SCP_SLED	SCP_LOAD	SCP_ACT	SCP_STP
7Ch	TempMon	R	CHIPTEMP _STATUS	CHIPTEMP
7Dh	Protect	R	TI Reserved
7Eh	Version	R	Version
7Fh	Status	R	ACTTIMER _FAULT	ENDDET	SIF _TIMEOUTERR	PWRERR	TSDERR	OCPSCPERR	TSDFAULT	FG
60h	Protect	R/W	TI Reserved
61h	SPM1	R/W	PWMmaxDuty_R_SEL1	TI Rsvd	OVP _SBRAKE _OFF	TI Reserved		SBRAKE _ON	TI Reserved
62h	SPM2	R/W	TI Reserved							PWMmaxDuty_R_SEL0
63h	Protect	R/W	TI Reserved
64h	Protect	R/W	TI Reserved
65h	Protect	R/W	TI Reserved
66h	Protect	R/W	TI Reserved
67h	Protect	R/W	TI Reserved
68h	Protect	R/W	TI Reserved
6Bh	DisProt	R/W	SCP_SPM _OFF	SCP_SLED _OFF	SCP_LOAD _OFF	SCP_ACT _OFF	SCP_STP _OFF	OCP_STP _OFF	TI Rsvd	OVPPRE12V_OFF
6Ch	STPCfg	R/W	TI Reserved			LDD_IUP		TI Rsvd	STP_WIND _HIZ	STP _WIND_H
6Dh	Protect	R/W	TI Reserved
6Eh	UtilCfg	R/W	GPOUT_HL	GPOUT _ENA	TI Reserved
6Fh	MonitorSet	R/W	ACTTIMER _FLT_MON	ENDDET _MON	SIF_TIMEOUTERR_MON	PWRERR _MON	TSDERR _MON	OCPERR _MON	TSDFAULT _MON	TI Rsvd

VTRK and VLOAD are exclusive, using same DAC circuit block.

8.6.4 Detailed Description of Registers

8.6.4.1 REG01 12-Bit DAC for Tilt (offset = 01h) [reset = ]

(VDAC_MAPSW = 0)

Figure 18. REG01 12-Bit DAC for Tilt

				11	10	9	8
				VTLT
				w-0	w-0	w-0	w-0

7	6	5	4	3	2	1	0
VTLT
w-0	w-0	w-0	w-0	w-0	w-0	w-0	w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. REG01 12-Bit DAC for Tilt Field Descriptions

Bit	Field	Type	Reset	Description
11-0	VTLT	W	0h	Digital input code for tilt 2’s complement format 0x800(-2048) to 0x7ff(+2047) Output is changed by differential tilt mode (REG74[7]) TLT_OUT = VTLT × (6.0 / 2048) (DIFF_TLT = 0) TLT_OUT = (VFCS – VTLT) × (6.0 / 2048) (DIFF_TLT = 1) TLT_OUT should be changed after writing VFCS. In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed after writing VFCS.

Bit

Field

Type

Reset

Description

11-0

VTLT

Digital input code for tilt

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Output is changed by differential tilt mode (REG74[7])

TLT_OUT = VTLT × (6.0 / 2048) (DIFF_TLT = 0)

TLT_OUT = (VFCS – VTLT) × (6.0 / 2048) (DIFF_TLT = 1)

TLT_OUT should be changed after writing VFCS.

In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed after writing VFCS.

8.6.4.2 REG02 12-Bit DAC for Focus (offset = 02h) [reset = ]

(VDAC_MAPSW=0)

Figure 19. REG02 12-Bit DAC for Focus

				11	10	9	8
				VFCS
				w-0	w-0	w-0	w-0

7	6	5	4	3	2	1	0
VFCS
w-0	w-0	w-0	w-0	w-0	w-0	w-0	w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. REG02 12-Bit DAC for Focus Field Descriptions

Bit	Field	Type	Reset	Description
11-0	VFCS	W	0h	Digital input code for focus 2’s complement format 0x800(-2048) to 0x7ff(+2047) Output is changed by differential tilt mode (REG74[7]) FCS_OUT = VFCS × (6.0 / 2048) (DIFF_TLT = 0) FCS_OUT = (VFCS + VTLT) × (6.0 / 2048) (DIFF_TLT = 1)

Bit

Field

Type

Reset

Description

11-0

VFCS

Digital input code for focus

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Output is changed by differential tilt mode (REG74[7])

FCS_OUT = VFCS × (6.0 / 2048) (DIFF_TLT = 0)

FCS_OUT = (VFCS + VTLT) × (6.0 / 2048) (DIFF_TLT = 1)

8.6.4.3 REG03 12-Bit DAC for Tracking (offset = 03h) [reset = ]

(VDAC_MAPSW=0)

Figure 20. REG03 12-Bit DAC for Tracking

				11	10	9	8
				VTRK
				w-0	w-0	w-0	w-0

7	6	5	4	3	2	1	0
VTRK
w-0	w-0	w-0	w-0	w-0	w-0	w-0	w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. REG03 12-Bit DAC for Tracking Field Descriptions

Bit	Field	Type	Reset	Description
11-0	VTRK	W	0h	Digital input code for tracking 2’s complement format 0x800(-2048) to 0x7ff(+2047) TRK_OUT = VTRK × (6.0 / 2048)

Bit

Field

Type

Reset

Description

11-0

VTRK

Digital input code for tracking

2’s complement format 0x800(-2048) to 0x7ff(+2047)

TRK_OUT = VTRK × (6.0 / 2048)

8.6.4.4 REG04 12-Bit DAC for Sled1 (offset = 04h) [reset = ]

(VDAC_MAPSW=0)

Figure 21. REG04 12-Bit DAC for Sled1

				11	10	9	8
				VSLD1
				w-0	w-0	w-0	w-0

7	6	5	4	3	2	1	0
VSLD1
w-0	w-0	w-0	w-0	w-0	w-0	w-0	w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. REG04 12-Bit DAC for Sled1 Field Descriptions

Bit	Field	Type	Reset	Description
11-0	VSLD1	W	0h	Digital input code for Sled1. 2’s complement format 0x800(-2048) to 0x7ff(+2047) Two bits on LSB, VSLD1[1:0], handled with zero. SLD1_OUT = VSLD1 × (880 mA / 2048)

Bit

Field

Type

Reset

Description

11-0

VSLD1

Digital input code for Sled1.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Two bits on LSB, VSLD1[1:0], handled with zero.

SLD1_OUT = VSLD1 × (880 mA / 2048)

8.6.4.5 REG05 12-Bit DAC for Sled2 (offset = 05h) [reset = ]

(VDAC_MAPSW=0)

Figure 22. REG05 12-Bit DAC for Sled2

				11	10	9	8
				VSLD2
				w-0	w-0	w-0	w-0

7	6	5	4	3	2	1	0
VSLD2
w-0	w-0	w-0	w-0	w-0	w-0	w-0	w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. REG05 12-Bit DAC for Sled2 Field Descriptions

Bit	Field	Type	Reset	Description
11-0	VSLD2	W	0h	Digital input code for Sled2. 2’s complement format 0x800(-2048) to 0x7ff(+2047) Two bits on LSB, VSLD2[1:0], are handled with zero. SLD2_OUT = VSLD2 × (880 mA/2048)

Bit

Field

Type

Reset

Description

11-0

VSLD2

Digital input code for Sled2.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Two bits on LSB, VSLD2[1:0], are handled with zero.

SLD2_OUT = VSLD2 × (880 mA/2048)

8.6.4.6 REG06 12-Bit DAC for Stepping1 (offset = 06h) [reset = ]

(VDAC_MAPSW = 0)

Figure 23. REG06 12-Bit DAC for Stepping1

				11	10	9	8
				VSTP1
				w-0	w-0	w-0	w-0

7	6	5	4	3	2	1	0
VSTP1
w-0	w-0	w-0	w-0	w-0	w-0	w-0	w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. REG06 12-Bit DAC for Stepping1 Field Descriptions

Bit	Field	Type	Reset	Description
11-0	VSTP1	W	0h	Digital input code for Stepping1 2’s complement format 0x800(-2048) to 0x7ff(+2047) Although VSTP1 is 12-bit width, MSB 8 bits is effective. Four bits on LSB, VSTP1[3:0], are handled with zero. VSTP1_OUT = VSTP1 × (P5V / 2048)

Bit

Field

Type

Reset

Description

11-0

VSTP1

Digital input code for Stepping1

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Although VSTP1 is 12-bit width, MSB 8 bits is effective.

Four bits on LSB, VSTP1[3:0], are handled with zero.

VSTP1_OUT = VSTP1 × (P5V / 2048)

8.6.4.7 REG07 12-Bit DAC for Stepping2 (offset = 07h) [reset = ]

(VDAC_MAPSW=0)

Figure 24. REG07 12-Bit DAC for Stepping2

				11	10	9	8
				VSTP2
				w-0	w-0	w-0	w-0

7	6	5	4	3	2	1	0
VSTP2
w-0	w-0	w-0	w-0	w-0	w-0	w-0	w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. REG07 12-Bit DAC for Stepping2 Field Descriptions

Bit	Field	Type	Reset	Description
11-0	VSTP2	W	0h	Digital input code for Stepping2 2’s complement format 0x800(-2048) to 0x7ff(+2047) Although VSTP2 is 12-bit width, MSB 8 bits is effective. Four bits on LSB, VSTP2[3:0], are handled with zero. VSTP2_OUT = VSTP2 × (P5V / 2048)

Bit

Field

Type

Reset

Description

11-0

VSTP2

Digital input code for Stepping2

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Although VSTP2 is 12-bit width, MSB 8 bits is effective.

Four bits on LSB, VSTP2[3:0], are handled with zero.

VSTP2_OUT = VSTP2 × (P5V / 2048)

8.6.4.8 REG08 12-Bit DAC for Spindle (offset = 08h) [reset = ]

(VDAC_MAPSW = 0)

Figure 25. REG08 12-Bit DAC for Spindle

				11	10	9	8
				VSPM
				w-0	w-0	w-0	w-0

7	6	5	4	3	2	1	0
VSPM
w-0	w-0	w-0	w-0	w-0	w-0	w-0	w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. REG08 12-Bit DAC for Spindle Field Descriptions

Bit	Field	Type	Reset	Description
11-0	VSPM	W	0h	Digital input code for Spindle 2’s complement format 0x800(-2048) to 0x7ff(+2047) SPM_OUT = VSPM × (14.0 / 2048)

Bit

Field

Type

Reset

Description

11-0

VSPM

Digital input code for Spindle

2’s complement format 0x800(-2048) to 0x7ff(+2047)

SPM_OUT = VSPM × (14.0 / 2048)

8.6.4.9 REG09 12-Bit DAC for Load (offset = 09h) [reset = ]

(VDAC_MAPSW = 0)

Figure 26. REG09 12-Bit DAC for Load

				11	10	9	8
				VLOAD
				w-0	w-0	w-0	w-0

7	6	5	4	3	2	1	0
VLOAD
w-0	w-0	w-0	w-0	w-0	w-0	w-0	w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. REG09 12-Bit DAC for Load Field Descriptions

Bit	Field	Type	Reset	Description
11-0	VLOAD	W	0h	Digital input code for Load. 2’s complement format 0x800(-2048) to 0x7ff(+2047) LOAD_OUT = VLOAD × (6.0 / 2048) at P5V12L = 5.0 V LOAD_OUT = VLOAD × (14.0/2048) at P5V12L = 12.0 V

Bit

Field

Type

Reset

Description

11-0

VLOAD

Digital input code for Load.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

LOAD_OUT = VLOAD × (6.0 / 2048) at P5V12L = 5.0 V

LOAD_OUT = VLOAD × (14.0/2048) at P5V12L = 12.0 V

8.6.4.10 REG0A 12-Bit DAC for Laser Diode Driver (offset = 0Ah) [reset = ]

(VDAC_MAPSW = 0)

Figure 27. REG0A 12-Bit DAC for Laser Diode Driver

				11	10	9	8
				VLDD
				w-0	w-0	w-0	w-0

7	6	5	4	3	2	1	0
VLDD
w-0	w-0	w-0	w-0	w-0	w-0	w-0	w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. REG0A 12-Bit DAC for Laser Diode Driver Field Descriptions

Bit	Field	Type	Reset	Description
11-0	VLDD	W	0h	Digital input code for VLDD. Since VLDD is 11 bit length, VLDD[11] should be set 0. Binary format 0x000 to 0x7ff(+2047) LDD_OUT = VLDD × (120 mA / 2048) MSB (bit 11) is secured in order to unite with other 12-bit form.

Bit

Field

Type

Reset

Description

11-0

VLDD

Digital input code for VLDD.

Since VLDD is 11 bit length, VLDD[11] should be set 0.

Binary format 0x000 to 0x7ff(+2047)

LDD_OUT = VLDD × (120 mA / 2048)

MSB (bit 11) is secured in order to unite with other 12-bit form.

8.6.4.11 REG70 8-Bit Control Register for DriverEna (offset = 70h) [reset = ]

Figure 28. REG70 8-Bit Control Register for DriverEna

7	6	5	4	3	2	1	0
TLT_ENA	FCS_ENA	TRK_ENA	SPM_ENA	SLD_ENA	STP_ENA	LOAD_ENA	XSLEEP
rw-0	rw-0	rw-0	rw-0	rw-0	rw-0	rw-0	rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. REG70 8-Bit Control Register for DriverEna Field Descriptions

Bit	Field	Type	Reset	Description
7	TLT_ENA	RW	0h	1h = Tilt enable (with XSLEEP = 1)
6	FCS_ENA	RW	0h	1h = Focus enable (with XSLEEP = 1)
5	TRK_ENA	RW	0h	1h = Track enable (with XSLEEP = 1)
4	SPM_ENA	RW	0h	1h = Spindle enable (with XSLEEP = 1)
3	SLD_ENA	RW	0h	1h = Sled enable (with XSLEEP = 1)
2	STP_ENA	RW	0h	1h = Step enable (with XSLEEP = 1)
1	LOAD_ENA	RW	0h	1h = LOAD enable (with XSLEEP = 1) Track (bit5:TRK_ENA) will be disabled at LOAD_ENA = 1 because of sharing the DAC PWM module. Load priority is higher than TRK_ENA.
0	XSLEEP	RW	0h	1h = Operation mode (need 1 ms) 0h = Power save mode Charge pump enable bit All driver enable bit (Bit[7:1]) change disabled and output change to Hi-Z (regardless of setting xxx_ENA bit is 1) when setting XSLEEP to 0. Therefore, set 1 to XSLEEP before setting each enable bits.

8.6.4.12 REG71 8-Bit Control Register for FuncEna (offset = 71h) [reset = ]

Figure 29. REG71 8-Bit Control Register for FuncEna

7	6	5	4	3	2	1	0
TI reserved	ENDDET_ENA	ENDDET_SEL		LDD_ENA	LDD_MSEL		TEMPMON _ENA
rw-0	rw-0	rw-0	rw-0	rw-0	rw-0		rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. REG71 8-Bit Control Register for FuncEna Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	RW	0h
6	ENDDET_ENA	RW	0h	1h = Use sled/step_End, load tray lock detection enable (with STP_ENA = 1, or SLD_ENA = 1, or LOAD_ENA = 1)
5-4	ENDDET_SEL	RW	0h	00 : Sled end detection monitor 01 : Step end detection monitor 10 : Load tray lock detection monitor
3	LDD_ENA	RW	0h	1h = LDD enable (with XSLEEP = 1)
2-1	LDD_MSEL	RW	0h	Laser diode driver output selection 00: No select 01: CD 10: DVD 11: BD
0	TEMPMON_ENA	RW	0h	1h = Enable chip temperature monitoring (with XSLEEP = 1)

8.6.4.13 REG72 8-Bit Control Register for ACTCfg (offset = 72h) [reset = ]

Figure 30. REG72 8-Bit Control Register for ACTCfg

7	6	5	4	3	2	1	0
P12VMUTE _NORST	RSTIN_OFF	ACTPROT _OFF	ACTTEMPTH
rw-0	rw-0	rw-0			rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. REG72 8-Bit Control Register for ACTCfg Field Descriptions

Bit	Field	Type	Reset	Description
7	P12VMUTE_NORST	RW	0h	0h = System reset at P12V low voltage 1h = Output High-Z only at P12V low voltage detection
6	RSTIN_OFF	RW	0h	0h = XRSTIN input enable 1h = Ignored XRSTIN pin input (do not reset device when XRSTIN = L)
5	ACTPROT_OFF	RW	0h	0h = Actuator protection ON 1h = Actuator fault monitor disable (no protection for ACT channel)
4-0	ACTTEMPTH	RW	0h	Actuator thermal protection (= ACT Timer) threshold level ACT Timer Protection enable except ACTTEMPTH[4:0] = 0x00 ACTTEMPTH = 0x00 equal to ACTPROT_OFF = 1 By writing value 0x00, ACTTIMER_PROT flag is cleared.

8.6.4.14 REG73 8-Bit Control Register for Parm0 (offset = 73h) [reset = ]

Figure 31. REG73 8-Bit Control Register for Parm0

7	6	5	4	3	2	1	0
SIF_TIMEOUT_TH		SLEDEND _HZTIME	SLDENDTH		STPEND _HZTIME	STPENDTH
rw-0		rw-0	rw-0		rw-0	rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. REG73 8-Bit Control Register for Parm0 Field Descriptions

Bit	Field	Type	Reset	Description
7-6	SIF_TIMEOUT_TH	RW	0h	Watch dog timer for serial communication 0h = disable 1h = 1 ms 2h = 100 µs 3h = 10 µs Set SIF_TIMEOUTERR (REG7D) if communication is suspended for this time period. Reset register processing is performed if a SIF_TIMEOUTERR occurs.
5	SLEDEND_HZTIME	RW	0h	Time window for sled end detection. 0h = 400 µs 1h = 200 µs Note: Need to recycle SLD_ENDDET_ENA = 0 → 1 after writing this bit.
4-3	SLDENDTH	RW	0h	Sled end detection sensibility setting. Detection threshold for motor BEMF 00: 124 mV 01: 168 mV 11: 73 mV　 10: 0 mV
2	STPEND_HZTIME	RW	0h	Step High-Z detection period in end detection 0h = 400 µs 1h = 200 µs Note: Need to recycle STP_ENDDET_ENA = 0 → 1 after writing this bit.
1-0	STPENDTH	RW	0h	Step end detection sensibility setting 00: 39 mV 01: 60 mV 11: 19 mV 10: 0 mV

8.6.4.15 REG74 8-Bit Control Register for SIFCfg (offset = 74h) [reset = ]

Figure 32. REG74 8-Bit Control Register for SIFCfg

7	6	5	4	3	2	1	0
DIFF_TLT	LDD_AMODE	RDSTAT _ON_VFCS	VSLD2_POL	VSTP2_POL	ADVANCE_RD	SOMI_HIZ	VDAC_MAPSW
rw-0	rw-0	rw-0	rw-0	rw-0	rw-0	rw-0	rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. REG74 8-Bit Control Register for SIFCfg Field Descriptions

Bit	Field	Type	Reset	Description
7	DIFF_TLT	RW	0h	1h = Differential tilt mode enable (with TLT_ENA = FCS_ENA = 1) Differential tilt mode (DIFF_TLT = 1), DAC value setting as follows FCS_OUT = (VFCS + VTLT) × 6 / 2048 TLT_OUT = (VFCS – VTLT) × 6 / 2048 In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed after writing VFCS.
6	LDD_AMODE	RW	0h	Setting LDD analog mode 0h = VLDD set by VDAC register (REG0A) 1h = VLDD set by voltage input via VLDDIN pin
5	RDSTAT_ON_VFCS	RW	0h	Set Read status data (REG7F) at VFCS write command (REG02) 1h = Enable Write and Read mode (Write 12 bits Focus DAC data + Read 8 bits status data)
4	VSLD2_POL	RW	0h	Change direction of SLED rotation
3	VSTP2_POL	RW	0h	Change direction of STEP rotation
2	ADVANCE_RD	RW	0h	0h = Normal read timing 1h = Read timing is advanced half clock cycle
1	SOMI_HIZ	RW	0h	0h = SOMI line High-Z at bus idling time. 1h = SOMI line pull down at bus idling time.
0	VDAC_MAPSW	RW	0h	1h = Change channel assignments of DAC register (REG01~0A)

8.6.4.16 REG75 8-Bit Control Register for Parm1 (offset = 75h) [reset = ]

Figure 33. REG75 8-Bit Control Register for Parm1

7	6	5	4	3	2	1	0
TRAY_LOCKDET			TI reserved		SPM_FAST _BRK	SPM_SLNT _BRK	SPM _HIZMODE
	rw-0		rw-0		rw-0	rw-0	rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. REG75 8-Bit Control Register for Parm1 Field Descriptions

Bit	Field	Type	Reset	Description
7-5	TRAY_LOCKDET	RW	0H	Load tray locking detection control 0h = Disable detection 1-7: Detection threshold 1h = 100 mA 2h = 150 mA 3h = 200 mA 4h = 250 mA 5h = 300 mA 6h = 350 mA 7h = 400 mA
4-3	Reserved	RW	0h
2	SPM_FAST_BRK	RW	0h	Fast brake mode selection 0h = Normal brake mode perform auto short brake sequence in specific speed 1h = No short brake under 5500 rpm
1	SPM_SLNT_BRK	RW	0h	Silent brake mode selection 0h = Normal brake mode 1h = No active brake under 5500 rpm Active brake mode is not performed inputting any value into VSPIN.
0	SPM_HIZMODE	RW	0h	Spindle output Hi-Z mode 0h = Normal operation 1h = Spindle output (UVW) put Hi-Z (use for test purpose)

8.6.4.17 REG76 8-Bit Control Register for WriteEna (offset = 76h) [reset = ]

Figure 34. REG76 8-Bit Control Register for WriteEna

7	6	5	4	3	2	1	0
WRITE _ENABLE	TI reserved						REG6X_Write
rw-0			rw-0				rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. REG76 8-Bit Control Register for WriteEna Field Descriptions

Bit

Field

Type

Reset

Description

WRITE_ENABLE

0h = Register Write disable except REG76

1h = Write enable for registers REG01~09, REG70~7F

6-1

Reserved

REG6X_Write

0h = Disable Write access REG6X bank

1h = Enable Write access REG6X bank

8.6.4.18 REG77 8-Bit Control Register for ClrReg (offset = 77h) [reset = ]

Figure 35. REG77 8-Bit Control Register for ClrReg

7	6	5	4	3	2	1	0
RST_INDAC	RST_REGS	RST_ERR _FLAG	TI reserved
w-0	w-0	w-0			w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. REG77 8-Bit Control Register for ClrReg Field Descriptions

Bit	Field	Type	Reset	Description
7	RST_INDAC	W	0h	1h = Reset all 12-bit input DAC register (REG01~09) *Self clear bit
6	RST_REGS	W	0h	1h = Reset all 8-bit R/W Registers (REG70h~77h, 60h-6Fh) *Self clear bit
5	RST_ERR_FLAG	W	0h	1h = Reset Fault Flag Latch (REG7F, REG79~REG7D) *Self clear bit
4-0	Reserved	W	0h

8.6.4.19 REG78 8-Bit Control Register for ActTemp (offset = 78h) [reset = ]

Figure 36. REG78 8-Bit Control Register for ActTemp

7	6	5	4	3	2	1	0
TI reserved		ACT_TIMER _PROT	ACTTEMP
r-0		r-0			r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. REG78 8-Bit Control Register for ActTemp Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

ACT_TIMER_PROT

ACT timer protection flag

1h = ACT timer protection has detected and latched.

(ACTTEMP > ACTTEMPTH)

This bit holds data after temperature change to low since this is a latch bit. Also driver output keep Hi-Z until setting RST_ERR_FLAG or ACTTEMPTH = 0.

4-0

ACTTEMP

An integrated value of ACT_TIMER counters at present

8.6.4.20 REG79 8-Bit Control Register for UVLOMon (offset = 79h) [reset = ]

Figure 37. REG79 8-Bit Control Register for UVLOMon

7	6	5	4	3	2	1	0
TI Reserved		UVLO_P5V	UVLO_INT3P3	UVLO_P12V	UVLO_SIOV	OVP_P5V	OVP_P12V
r-0	r-0	r-0	r-0	r-0	r-0	r-0	r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. REG79 8-Bit Control Register for UVLOMon Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R	0h
5	UVLO_P5V	R	0h	UVLO flag for detection Low P5V supply ⁽¹⁾
4	UVLO_INT3P3	R	0h	UVLO flag for detection Low internal 3.3 V regulator⁽¹⁾
3	UVLO_P12V	R	0h	UVLO flag for detection Low P12V supply ⁽¹⁾
2	UVLO_SIOV	R	0h	UVLO flag for detection Low SIOV supply ⁽¹⁾
1	OVP_P5V	R	0h	Overvoltage protection flag for P5V supply ⁽¹⁾
0	OVP_P12V	R	0h	Overvoltage protection flag for P12V supply ⁽¹⁾

(1) Latched first reset event only. Cleared by RST_ERR_FLG (REG77)

8.6.4.21 REG7A 8-Bit Control Register for TSDMon (offset = 7Ah) [reset = ]

Figure 38. REG7A 8-Bit Control Register for TSDMon

7	6	5	4	3	2	1	0
TI reserved	TSD_FAULT _SPM	TSD_FAULT _ACT	TSD_FAULT _LDD	TI reserved	TSD_SPM	TSD_ACT	TSD_ LDD
r-0	r-0	r-0	r-0	r-0	r-0	r-0	r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. REG7A 8-Bit Control Register for TSDMon Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R	0h
6	TSD_FAULT_SPM	R	0h	Pre alert of thermal protection of Spindle block⁽¹⁾
5	TSD_FAULT_ACT	R	0h	Pre alert of thermal protection of focus, track, tilt, sled1, sled2, step1, step2, load⁽¹⁾
4	TSD_FAULT_LDD	R	0h	Prealert of thermal protection of LDD⁽¹⁾
3	Reserved	R	0h
2	TSD_SPM	R	0h	Thermal protection flag for Spindle⁽¹⁾ SPM output Hi-Z until temperature falls on release level 1h = Detect (latch)
1	TSD_ACT	R	0h	Thermal protection flag for focus, track, tilt, sled1, sled2, step1, step2, load⁽¹⁾ Actuator output Hi-Z until temperature falls on release level 1h = Detect (latch)
0	TSD_ LDD	R	0h	Thermal protection flag for LDD⁽¹⁾ LDD output Hi-Z until temperature falls on release level 1h = Detect (latch)

(1) Cleared by RST_ERR_FLAG bit (REG77)

8.6.4.22 REG7B 8-Bit Control Register for OCPMon (offset = 7Bh) [reset = ]

Figure 39. REG7B 8-Bit Control Register for OCPMon

7	6	5	4	3	2	1	0
TI reserved		OCP_STP	SCP_SPM	SCP_SLED	SCP_LOAD	SCP_ACT	SCP_STP
	r-0		r-0	r-0	r-0	r-0	r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. REG7B 8-Bit Control Register for OCPMon Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R	0h
5	OCP_STP	R	0h	Overcurrent protection flag bit for step block⁽¹⁾
4	SCP_SPM	R	0h	Short protection flag bit for spindle block⁽¹⁾
3	SCP_SLED	R	0h	Short protection flag bit for sled block⁽¹⁾
2	SCP_LOAD	R	0h	Short protection flag bit for load block⁽¹⁾
1	SCP_ACT	R	0h	Short protection flag bit for actuator block⁽¹⁾
0	SCP_STP	R	0h	Short protection flag bit for step block⁽¹⁾

(1) Cleared by RST_ERR_FLAG bit (REG77)

8.6.4.23 REG7C 8-Bit Control Register for TempMon (offset = 7Ch) [reset = ]

Figure 40. REG7C 8-Bit Control Register for TempMon

7	6	5	4	3	2	1	0
TI Reserved	CHIPTEMP _STATUS	CHIPTEMP
r-0	r-0			r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. REG7C 8-Bit Control Register for TempMon Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

CHIPTEMP_STATUS

1h = New data CHIPTEMP[5:0] is updated It will be cleared after reading.

5-0

CHIPTEMP

Chip temperature monitor (2.38°/LSB)

15(0) to 165(63) degrees.

For monitoring, TEMPMON_ENA = 1 and XSLEEP = 1 is required

8.6.4.24 REG7E 8-Bit Control Register for Version (offset = 7Eh) [reset = ]

Figure 41. REG7E 8-Bit Control Register for Version

7	6	5	4	3	2	1	0
Version
			r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. REG7E 8-Bit Control Register for Version Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Version

Version[7:4] = Revision number of TPIC2050

Version[3:0] = Option

8.6.4.25 REG7F 8-Bit Control Register for Status (offset = 7Fh) [reset = ]

Figure 42. REG7F 8-Bit Control Register for Status

7	6	5	4	3	2	1	0
ACTTIMER _FAULT	ENDDET	SIF_TIMEOUTERR	PWRERR	TSDERR	OCPERR	TSDFAULT	FG
r-0	r-0	r-0	r-0	r-0	r-0	r-0	r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. REG7F 8-Bit Control Register for Status Field Descriptions

Bit	Field	Type	Reset	Description
7	ACTTIMER_FAULT	R	0h	Status flag of ACTTIMER protection 1h = Prealert of ACTTIMER protection. It is close to the threshold level. The user can get the current ACTTIMER value in REG78. Both this bit and ACT_TIMER_PROT (REG78) are set when over the threshold.
6	ENDDET	R	0h	Status flag of END detection 1h = End position detected (not latch bit) for step/sled. (ENDDET_SEL = 10) Load motor current exceeds threshold at using load tray lock detection. (ENDDET_SEL = 10)
5	SIF_TIMEOUTERR	R	0h	Error flag of serial interface watch dog timer 1h = SIF communication was interrupted, expired watch dog timer
4	PWRERR	R	0h	Error flag of power 1h = Voltage problem occurred, details in REG79
3	TSDERR	R	0h	Error flag of any overthermal protections 1h = Dispatched thermal protection, details in REG7A
2	OCPERR	R	0h	Error flag of any short-circuit protection 1h = Dispatched SCP, details in REG7Bh
1	TSDFAULT	R	0h	Warning of TSD of any thermal protection 1h = Detect pre thermal protection, details in REG7A
0	FG	R	0h	FG signal. Spindle rotation pulse for speed monitor

8.6.4.26 REG61 8-Bit Control Register for SPM1 (offset = 61h) [reset = ]

Figure 43. REG61 8-Bit Control Register for SPM1

7	6	5	4	3	2	1	0
PWMmaxDuty _R_SEL1	TI reserved	OVP_SBRAKE _OFF	TI reserved		SBRAKE_ON	TI reserved
rw-0	rw-0	rw-0	rw-0		rw-0	rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. REG61 8-Bit Control Register for SPM1 Field Descriptions

Bit	Field	Type	Reset	Description
7	PWMmaxDuty_R_SEL1	RW	0h	PWM duty maximum setting in active brake mode (upper bit of PWMmaxDuty_R_SEL[1:0]) 00: Maximum PWM duty 12.5% 　 01: Maximum PWM duty 25% 10: Maximum PWM duty 37.5% 11: Maximum PWM duty 37.5% (TI recommends to set to 0X in case of use in no-disk, because it may not stop in a specific motor setting 37.5%.)
6	Reserved	RW	0h
5	OVP_SBRAKE_OFF	RW	0h	Select short brake mode of P12V pre-OVP 0h = 3-phase short brake mode 1h = 2-phase short brake mode
4-3	Reserved	RW	0h
2	SBRAKE_ON	RW	0h	Force short brake 0h = No brake 1h = Perform 3-phase short brake in any state
1-0	Reserved	RW	0h

8.6.4.27 REG62 8-Bit Control Register for SPM2 (offset = 62h) [reset = ]

Figure 44. REG62 8-Bit Control Register for SPM2

7	6	5	4	3	2	1	0
TI reserved							PWMmaxDuty _R_SEL0
	rw-0			rw-0		rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. REG62 8-Bit Control Register for SPM2 Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	RW	0h
0	PWMmaxDuty_R_SEL0	RW	0h	PWM duty maximum setting in active brake mode (lower bit of PWMmaxDuty_R_SEL[1:0])

8.6.4.28 REG6B 8-Bit Control Register for DisProt (offset = 6Bh) [reset = ]

Figure 45. REG6B 8-Bit Control Register for DisProt

7	6	5	4	3	2	1	0
SCP_SPM _OFF	SCP_SLED _OFF	SCP_LOAD _OFF	SCP_ACT _OFF	SCP_STP_OFF	OCP_STP _OFF	TI reserved	OVPPRE12V _OFF
rw-0	rw-0	rw-0	rw-0	rw-0	rw-0	rw-0	rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. REG6B 8-Bit Control Register for DisProt Field Descriptions

Bit	Field	Type	Reset	Description
7	SCP_SPM_OFF	RW	0h	Control bit of short-circuit protection function for spindle block 0h = Enable SCP function 1h = Disable SCP function Caution⁽¹⁾: TI recommends using it only for test purposes.
6	SCP_SLED_OFF	RW	0h	For sled driver block Caution⁽¹⁾: TI recommends using it only for test purposes.
5	SCP_LOAD_OFF	RW	0h	For load driver block Caution⁽¹⁾: TI recommends using it only for test purposes.
4	SCP_ACT_OFF	RW	0h	For actuator driver block Caution⁽¹⁾: TI recommends using it only for test purposes.
3	SCP_STP_OFF	RW	0h	For step driver block Caution⁽¹⁾: TI recommends using it only for test purposes.
2	OCP_STP_OFF	RW	0h	Control bit of overcurrent protection function for stepper block 0h = Enable OCP function 1h = Disable OCP function Caution⁽¹⁾: TI recommends using it only for test purpose.
1	Reserved	RW	0h
0	OVPPRE12V_OFF	RW	0h	Disable short brake function at P12V pre-OVP condition. 0h = Enable function which perform short brake at 12-V pre-OVP 1h = Disable short brake at 12-V pre-OVP TI recommend to set to 0

(1) CAUTION: Device will be fatally damaged if short circuit occurs in the xxx_OFF = 1.

8.6.4.29 REG6C 8-Bit Control Register for STPCfg (offset = 6Ch) [reset = ]

Figure 46. REG6C 8-Bit Control Register for STPCfg

7	6	5	4	3	2	1	0
TI Reserved			LDD_IUP		TI Reserved	STP_WIND _HIZ	STP_WIND_H
	rw-0	rw-0			rw-0	rw-0	rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. REG6C 8-Bit Control Register for STPCfg Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	RW	0h
4-3	LDD_IUP	RW	0h	Extend LDD maximum current 00: 120 mA 01: 1.24× an initial value 10: 1.48× an initial value (1) 11: 1.72× an initial value (2) 1) The LDD output time of the maximum current should maintain 50% or less of the xsleep total ON time. 2) The LDD output time of the maximum current should maintain 25% or less of the xsleep total ON time.
2	Reserved	RW	0h
1	STP_WIND_HIZ	RW	0h	0h = Normal end detection 1h = When detecting BEMF, set STP1 and STP2 FET Hi-Z to reduce mutual noise.
0	STP_WIND_H	RW	0h	0h = Normal end detection 1h = When detecting BEMF, set driving phase to Hi (detecting phase Hi-Z) to reduce mutual noise.

8.6.4.30 REG6E 8-Bit Control Register for UtilCfg (offset = 6Eh) [reset = ]

Figure 47. REG6E 8-Bit Control Register for UtilCfg

7	6	5	4	3	2	1	0
GPOUT_HL	GPOUT_ENA	TI reserved
rw-0	rw-0			rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. REG6E 8-Bit Control Register for UtilCfg Field Descriptions

Bit

Field

Type

Reset

Description

GPOUT_HL

GPOUT (general-purpose output) pin output selection

0h = Low output

1h = High output

Valid only if REG6F = 00h

GPOUT_ENA

Enable monitor signal output to GPOUT pin

0h = No signal output, Hi-Z

1h = Output signal selected in REG6F with CMOS output

Output is logical OR when selected two more signals

5-0

Reserved

8.6.4.31 REG6F 8-Bit Control Register for MonitorSet (offset = 6Fh) [reset = ]

Figure 48. REG6F 8-Bit Control Register for MonitorSet

7	6	5	4	3	2	1	0
ACTTIMER _FLT_MON	ENDDET _MON	SIF _TIMEOUTERR _MON	PWRERR _MON	TSDERR_MON	OCPERR _MON	TSDFAULT _MON	TI Rsvd
rw-0	rw-0	rw-0	rw-0	rw-0	rw-0	rw-0	rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 38. REG6F 8-Bit Control Register for MonitorSet Field Descriptions

Bit	Field	Type	Reset	Description
7	ACTTIMER_FLT_MON	RW	0h	1h = ACTTIMER fault output to GPOUT pin
6	MONITOR_MON	RW	0h	1h = ENDDET monitor output to GPOUT pin
5	SIF_TIMEOUTERR_MON	RW	0h	1h = SIF timeout monitor output to GPOUT pin
4	PWRERR_MON	RW	0h	1h = PWRERR monitor output to GPOUT pin
3	TSDERR_MON	RW	0h	1h = TSDERR fault output to GPOUT pin
2	SCPERR_MON	RW	0h	1h = OCPERR fault output to GPOUT pin
1	TSDFAULT_MON	RW	0h	1h = TSDFAULT fault output to GPOUT pin
0	Reserved	RW	0h