JAJSC11D October   2014  – December 2019 TPS1H100-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements – Current Sense Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Accurate Current Sense
      2. 7.3.2 Programmable Current Limit
      3. 7.3.3 Inductive-Load Switching-Off Clamp
      4. 7.3.4 Full Protections and Diagnostics
        1. 7.3.4.1  Short-to-GND and Overload Detection
        2. 7.3.4.2  Open-Load Detection
        3. 7.3.4.3  Short-to-Battery Detection
        4. 7.3.4.4  Reverse-Polarity Detection
        5. 7.3.4.5  Thermal Protection Behavior
        6. 7.3.4.6  UVLO Protection
        7. 7.3.4.7  Loss of GND Protection
        8. 7.3.4.8  Loss of Power Supply Protection
        9. 7.3.4.9  Reverse Current Protection
        10. 7.3.4.10 Protection for MCU I/Os
      5. 7.3.5 Diagnostic Enable Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Working Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Distinguishing of Different Fault Modes
        2. 8.2.2.2 AEC Q100-012 Test Grade A Certification
        3. 8.2.2.3 EMC Transient Disturbances Test
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Without a GND Network
      2. 10.2.2 With a GND Network
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4.5 Thermal Protection Behavior

Both the absolute temperature thermal shutdown and the dynamic temperature thermal swing diagnostic and protection are built into the device to increase the maximum reliability of the power FET. Thermal swing is active when the temperature of the power FET is increasing sharply, that is ΔT = TDMOS – TLogic > Tsw, then the output is shut down, and the ST pin goes low, or the CS pin is pulled up to VCS,h. It auto-recovers and clears the fault signal until ΔT = TDMOS – TLogic < Tsw – Thys. Thermal swing function improves device reliability against repetitive fast thermal variation, as shown in Figure 37. Multiple thermal swings are triggered before thermal shutdown happens. Thermal shutdown is active when absolute temperature T > TSD. When active, the output is shut down, and the ST pin goes low, or the CS pin is pulled up to VCS,h. The output is auto-recovered when T < TSD – Thys; the current limit is reduced to Ilim,tsd, or half of the programmable current limit value, to avoid repeated thermal shutdown. However, the thermal shutdown fault signal and half-current limit value are not cleared until the junction temperature decreases to less than TSD,rst.

TPS1H100-Q1 themal_prot_lvscm2.gifFigure 37. Thermal Behavior