JAJSCJ4A September   2016  – October 2016 TPS254900-Q1


  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  FAULT Response
      2. 8.3.2  Cable Compensation
        1. Design Procedure
      3. 8.3.3  D+ and D- Protection
      4. 8.3.4  VBUS OVP Protection
      5. 8.3.5  Output and D+ or D- Discharge
      6. 8.3.6  Port Power Management (PPM)
        1. Benefits of PPM
        2. PPM Details
        3. Implementing PPM in a System With Two Charging Ports (CDP and SDP1)
      7. 8.3.7  Overcurrent Protection
      8. 8.3.8  Undervoltage Lockout
      9. 8.3.9  Thermal Sensing
      10. 8.3.10 Current-Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 USB BC1.2 Specification Overview
      3. 8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0
      4. 8.4.4 Charging Downstream Port (CDP) Mode
      5. 8.4.5 Client Mode
      6. 8.4.6 High-Bandwidth Data-Line Switch
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Input Capacitance
        2. Output Capacitance
        3. BIAS Capacitance
        4. Output and BIAS TVS
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報




Layout Guidelines

Layout best practices for the TPS254900-Q1 are listed as follows.

  • Considerations for input and output power traces
    • Make the power traces as short as possible.
    • Make the power traces as wide as possible.
  • Considerations for input-capacitor traces
    • For all applications, 10-µF and 0.1-µF low-ESR ceramic capacitors are recommended, placed close to the IN pin.
  • The resistors attached to the ILIM_HI and ILIM_LO pins of the device have several requirements.
    • It is recommended to use 1% low-temperature-coefficient resistors.
    • The trace routing between these two pins and GND should be as short as possible to reduce parasitic effects on current limit. These traces should not have any coupling to switching signals on the board.
  • Locate all TPS254900-Q1 pullup resistors for open-drain outputs close to their connection pin. Pullup resistors should be 100 kΩ.
    • If a particular open-drain output is not used or needed in the system, tie it to GND.
  • ESD considerations
    • The TPS254900-Q1 device has built-in ESD protection for DP_IN and DM_IN. Keep trace lengths minimal from the USB connector to the DP_IN and DM_IN pins on the TPS254900-Q1 device, and use minimal vias along the traces.
    • The capacitor on BIAS helps to improve the IEC ESD performance. A 2.2-µF capacitor should be placed close to BIAS, and the current path from BIAS to GND across this capacitor should be as short as possible. Do not use vias along the connection traces.
    • A 10-µF output capacitor should be placed close to the OUT pin and TVS.
    • See the ESD Protection Layout Guide (SLVA680) for additional information.
  • TVS Considerations
    • For OUT, a TVS like SMAJ18 should be placed near the OUT pin.
    • For BIAS, a TVS like SMAJ18 should be placed close to the BIAS pin, but behind the 2.2-µF capacitor.
    • The whole path from OUT to GND or BIAS to GND across the TVS should be as short as possible.
  • DP_IN, DM_IN, DP_OUT, and DM_OUT routing considerations
    • Route these traces as microstrips with nominal differential impedance of 90 Ω.
    • Minimize the use of vias on the high-speed data lines.
    • Keep the reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities.
    • For more USB 2.0 high-speed D+ and D– differential routing information, see the High Speed USB Platform Design Guideline from Intel.
  • Thermal Considerations
    • When properly mounted, the thermal-pad package provides significantly greater cooling ability than an ordinary package. To operate at rated power, the thermal pad must be soldered to the board GND plane directly under the device. The thermal pad is at GND potential and can be connected using multiple vias to inner-layer GND. Other planes, such as the bottom side of the circuit board, can be used to increase heat sinking in higher-current applications. See the PowerPad™ Thermally Enhanced Package application report (SLMA002) and PowerPAD™ Made Easy application brief (SLMA004) for more information on using this thermal pad package.

Layout Example

TPS254900-Q1 Layout_SLUSCO9.gif Figure 54. TPS254900-Q1 Layout Diagram