JAJSE35C November   2017  – August 2019 TPS25820 , TPS25821

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 USB Type C Basic
      2. 7.1.2 Configuration Channel
      3. 7.1.3 Detecting a Connection
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Configuration Channel Pins CC1 and CC2
      2. 7.3.2 Current Capability Advertisement and VBUS Overload Protection
      3. 7.3.3 FAULT Response
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 REF
      6. 7.3.6 Plug Polarity Detection
      7. 7.3.7 Sink Attachment Indicator
      8. 7.3.8 Device Enable Control
      9. 7.3.9 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Type-C Source Port Implementation without BC 1.2 Support
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input and Output Capacitance Considerations
          2. 8.2.1.1.2 System Level ESD Protection
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Type -C Source Port Implementation with BC 1.2 (DCP Mode) Support
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Implementing a USB 3.1 Type-C Charging Port with the TPS25820
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
      4. 8.2.4 Implementing TPS25821 in USB Car Chargers
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1 Layout Guidelines

Layout best practices as it applies to the TPS25820/21 are listed below.

  • For all applications a ceramic capacitor less than 10 µF is recommended near the Type-C receptacle and another 120-µF ceramic capacitor placed close to the IN pin.
    • The optimum placement of the 120-µF capacitor is closest to the IN and GND pins of the device.
    • Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC. See Figure 22 for a PCB layout example.
  • High current carrying power path connections to the device should be as short as possible and should be sized to carry at least twice the full-load current.
    • Have the input and output traces as short as possible. The most common cause of voltage drop failure in USB power delivery is the resistance associated with the VBUS trace. Trace length, maximum current being supplied for normal operation, and total resistance associated with the VBUS trace must be taken into account while budgeting for voltage drop.
    • For example, a power carrying trace that supplies 1.5 A, at a distance of 20 inches, 0.100-in. wide, with 2-oz. copper on the outer layer will have a total resistance of approximately 0.046 Ω and voltage drop of 0.07 V. The same trace at 0.050-in.-wide will have a total resistance of approximately 0.09 Ω and voltage drop of 0.14 V.
    • Make power traces as wide as possible.
  • The resistor attached to the REF pin of the device has several requirements:
    • It is recommended to use a 0.5% 100-kΩ resistor.
    • It should be connected to pins REF and GND.
    • The trace routing between the REF and GND pins of the device should be as short as possible to reduce parasitic effects on the current limit and current advertisement accuracy. These traces should not have any coupling to switching signals on the board.
  • Locate all TPS25820/21 pull-up resistors for open-drain outputs close to their connection pin. Pull-up resistors should be 100 kΩ.
    • When a particular open drain output is not used/needed in the system leave the associated pin open or tied to GND.
  • Keep the CC lines close to the same length.
  • Thermal Considerations:
    • When properly mounted, the thermal pad package provides significantly greater cooling ability than an ordinary package. To operate at rated power, the thermal pad must be soldered to the board GND plane directly under the device. The thermal pad is at GND potential and can be connected using multiple vias to inner layer GND. Other planes, such as the bottom side of the circuit board can be used to increase heat sinking in higher current applications. Refer to Technical Briefs: PowerPad™ Thermally Enhanced Package (TI literature Number SLMA002) and PowerPAD™ Made Easy (TI Literature Number SLMA004) or more information on using this thermal pad package.
    • The thermal via land pattern specific to the TPS25820/21 can be downloaded from the device web page at www.ti.com.
    • Obtaining acceptable performance with alternate layout schemes is possible; however the layout example in the following section has been shown to produce good results and is intended as a guideline.