JAJSBS5G February   2012  – February 2019 TPS3700

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      出力と入力のスレッショルドとヒステリシスの関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inputs (INA+, INB–)
      2. 7.3.2 Outputs (OUTA, OUTB)
      3. 7.3.3 Window Voltage Detector
      4. 7.3.4 Immunity to Input Terminal Voltage Transients
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > UVLO)
      2. 7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 7.4.3 Power-On Reset (VDD < V(POR))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 VPULLUP to a Voltage Other Than VDD
      2. 8.1.2 Monitoring VDD
      3. 8.1.3 Monitoring a Voltage Other Than VDD
      4. 8.1.4 Monitoring Overvoltage and Undervoltage for Separate Rails
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Resistor Divider Selection
        2. 8.2.2.2 Pullup Resistor Selection
        3. 8.2.2.3 Input Supply Capacitor
        4. 8.2.2.4 Input Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 評価基板
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DSE|6
  • DDC|6
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over the operating temperature range of TJ = –40°C to 125°C, and 1.8 V < VDD < 18 V, unless otherwise noted.
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Supply voltage range 1.8 18 V
V(POR) Power-on reset voltage(1) VOLmax = 0.2 V, I(OUTA/B) = 15 µA 0.8 V
VIT+ Positive-going input threshold voltage VDD = 1.8 V 396 400 404 mV
VDD = 18 V 396 400 404
VIT– Negative-going input threshold voltage VDD = 1.8 V 387 394.5 400 mV
VDD = 18 V 387 394.5 400
Vhys Hysteresis voltage (hys = VIT+ – VIT–) 5.5 12
I(INA+) Input current (at the INA+ terminal) VDD = 1.8 V and 18 V, VI = 6.5 V –25 1 25 nA
I(INB–) Input current (at the INB– terminal) VDD = 1.8 V and 18 V, VI = 0.1 V –15 1 15 nA
VOL Low-level output voltage VDD = 1.3 V, IO = 0.4 mA 250 mV
VDD = 1.8 V, IO = 3 mA 250
VDD = 5 V, IO = 5 mA 250
Ilkg(OD) Open-drain output leakage-current VDD = 1.8 V and 18 V, VO = VDD 300 nA
VDD = 1.8 V, VO = 18 V 300
IDD Supply current VDD = 1.8 V, no load 5.5 11 µA
VDD = 5 V 6 13
VDD = 12 V 6 13
VDD = 18 V 7 13
Start-up delay(2) 150 450 µs
UVLO Undervoltage lockout(3) VDD falling 1.3 1.7 V
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
(2) During power on, VDD must exceed 1.8 V for 450 µs (max) before the output is in a correct state.
(3) When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR).